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Agarwal, Shri

Publications and source records attributed to Agarwal, Shri.

At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2014

Aeroflex Technology as Class-Y Demonstrator

Modern space field programmable gate array (FPGA) devices with increased functional density and operational frequency, such as Xilinx Virtex 4 (V4) and S (V5), are packaged in non-hermetic ceramic flip chip forms. These next generation space parts were not qualified to the MIL-PRF-38535 Qualified Manufacturer Listing (QML) class-V when they were released because class-V was only intended for hermetic parts. In order to bring Xilinx V5 type packages into the QML system, it was suggested that class-Y be set up as a new category. From 2010 through 2014, a JEDEC G12 task group developed screening and qualification requirements for Class-Y products. The Document Standardization Division of the Defense Logistics Agency (DLA) has completed an engineering practice study. In parallel with the class-Y efforts, the NASA Electronic Parts and Packaging (NEPP) program has funded JPL to study potential reliability issues of the class-Y products. The major hurdle of this task was the absence of adequate research samples. Figure 1-1 shows schematic diagrams of typical structures of class-Y type products. Typically, class-Y products are either in ceramic flip chip column grid array (CGA) or land grid array (LGA) form. In class-Y packages, underfill and heat spread adhesive materials are directly exposed to the spacecraft environment due to their non-hermeticity. One of the concerns originally raised was that the underfill material could degrade due to the spacecraft environment and negatively impact the reliability of the package. In order to study such issues, it was necessary to use ceramic daisy chain flip chip package samples so that continuity of flip chip solder bumps could be monitored during the reliability tests. However, none of the commercially available class-Y daisy chain parts had electrical connections through flip chip solder bumps; only solder columns were daisy chained, which made it impossible to test continuity of flip chip solder bumps without using extremely costly functional parts. Among space parts manufacturers who were interested in producing class-Y products, Aeroflex Microelectronic Solutions-HiRel had been developing assembly processes using their internal R&D classy type samples. In early 2012, JPL and Aeroflex initiated a collaboration to study reliability of the Aeroflex technology as a class-Y demonstrator.

Suh, Jong-ook↗
NASA NTRS2012

NASA Electronic Parts and Packaging (NEPP) Program

Recent Findings from Audits, New Technology Data Reviews a) Disabled Chip Burn-ins A recent audit for a QML device discovered that the chip was disabled during the static burn-in, thus it was not drawing any current. Recommendation: For new SMDs add a statement within the burn-in paragraphs stating that the parts shall be kept in their enabled state during the burn-in. b) Class Q 160-hr/125oC Burn-in This is being interpreted as a static burn-in (even for CMOS technology). Recommendation: Provide clarification in MIL-STD-883, Test Method 5004. c) At Frequency (Dynamic) Burn-ins Test equipment limitation is being cited for not doing burn-ins at the application frequency. Recommendation: The burn-in task group to discuss and provide guidance. When the SMD says that the part can be used at 200 MHz, then doing burn-in at 6 MHz (cited as burn-in equipment limitation frequency) is not going to be meaningful! d) Two Static Burn-ins Some manufacturers are doing electrical testing between the two static burn-ins, whereas others do electricals after completing both static burn-ins. Recommendation: Provide clarification in MIL-STD-883, Test Method 5004. e) Thermal Imaging For a device with hot spots, the thermal resistance, junction-to-case, would be much higher than the guidelines given in MIL-STD-1835. One of the suppliers used thermal imaging to find hot spots on the die. Recommendation: Assign a task group to evaluate the effectiveness of thermal imaging at the product development stage.

Class Y↗
NASA NTRS2012

Infusion of New Technology into the QML System

QML stands for the Qualified Manufacturer List. It is maintained by DLA-Land and Maritime (formerly known as the Defense Supply Center Columbus, DSCC). This talk will address how we are bringing new technology products into the QML system. The focus will be on microcircuit parts used in space application. A new effort championed by NASA will be described. NASA EEE Parts Assurance Group (NEPAG) is making every effort to strengthen the MIL system and thereby support the space flight projects

Class Y↗
NASA NTRS2005

CSAM Metrology Software Tool

CSAM Metrology Software Tool (CMeST) is a computer program for analysis of false-color CSAM images of plastic-encapsulated microcircuits. (CSAM signifies C-mode scanning acoustic microscopy.) The colors in the images indicate areas of delamination within the plastic packages. Heretofore, the images have been interpreted by human examiners. Hence, interpretations have not been entirely consistent and objective. CMeST processes the color information in image-data files to detect areas of delamination without incurring inconsistencies of subjective judgement. CMeST can be used to create a database of baseline images of packages acquired at given times for comparison with images of the same packages acquired at later times. Any area within an image can be selected for analysis, which can include examination of different delamination types by location. CMeST can also be used to perform statistical analyses of image data. Results of analyses are available in a spreadsheet format for further processing. The results can be exported to any data-base-processing software.

Vu, Duc↗