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Alkalaj, Leon

Publications and source records attributed to Alkalaj, Leon.

11 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1998

Electronic processing and control system with programmable hardware

A computer system with reprogrammable hardware allowing dynamically allocating hardware resources for different functions and adaptability for different processors and different operating platforms. All hardware resources are physically partitioned into system-user hardware and application-user hardware depending on the specific operation requirements. A reprogrammable interface preferably interconnects the system-user hardware and application-user hardware.

Alkalaj, Leon↗
NASA NTRS1996

A microelectronics approach for the ROSETTA surface science package

In relation to the Rosetta surface science package, the benefits of the application of advanced microelectronics packaging technologies and other output from the Mars environmental survey (MESUR) integrated microelectronics study are reported on. The surface science package will be designed to operate for tens of hours. Its limited mass and power consumption make necessary a highly integrated design with all the instruments and subunits operated from a centralized control and information management subsystem.

Sandau, Rainer↗
NASA NTRS1995

Architecture Of A Sciencecraft To Fly Past Pluto

Two reports discuss architecture of proposed small sciencecraft carrying scientific instruments on trajectory passing near Pluto and continuing into interstellar space. Emphasizes those aspects of design pertaining to compactness, efficiency, and small mass (dry mass less than 100 kg). System block diagram of sciencecraft divided into blocks for sensors, integrated microelectronics, and motive effectors.

Price, Humphrey W.↗
NASA NTRS1995

Compact Multimedia Systems in Multi-chip Module Technology

This tutorial paper shows advanced multimedia system designs based on multi-chip module (MCM) technologies that provide essential computing, compression, communication, and storage capabilities for various large scale information highway applications.!.

Multi-Chip Module Technology↗
NASA NTRS1994

(abstract) Automated Constraint Checking of Spacecraft Command Sequences

Making certain that spacecraft command sequences do not violate any constraints is often tedious and expensive in terms of both personnel and software development. To reduce this cost, we have pursued the development of a flexible system for specifying models of spacecraft behavior in response to commands as well as constraints on that behavior. The potential need for modeling complex spacecraft behavior required that the system be designed to be usable both on a conventional workstation and a parallel supercomputer. Finally, it needed to be intuitive enough for the the intended mission operations users to easily design sets of rules and models to automate tedious, resource-consuming constraint checking of commands. We have defined a Specification And Verification Environment (SAVE) for spacecraft flight rules.

automation spacecraft command sequences constraint↗
NASA NTRS1993

(abstract) The Nest Generation of Space Flight Computers

To meet new design objectives for drastic reductions in mass, size, and power consumption, the Flight Computer Development Group at JPL is participating in a design study and development of a light-weight, small-sized, low-power 3-D Space Flight Computer. In this paper, we will present a detailed design and tradeoff study of the proposed computer. We will also discuss a complete design of the multichip modules and their size, weight, and power consumption. Prelimimary thermal models will also be discussed.

space flight computers design power consumption ma↗
NASA NTRS1993

Power optimization in logic isomers

Logic isomers are labeled, 2-isomorphic graphs that implement the same logic function. Logic isomers may have significantly different power requirements even though they have the same number of transistors in the implementation. The power requirements of the isomers depend on the transition activity of the input signals. The power requirements of isomorphic graph isomers of n-input NAND and NOR gates are shown. Choosing the less power-consuming isomer instead of the others can yield significant power savings. Experimental results on a ripple-carry adder are presented to show that the implementation using the least power-consuming isomers requires approximately 10 percent less power than the implementation using the most power-consuming isomers. Simulations of other random logic designs also confirm that designs using less power-consuming isomers can reduce the logic power demand by approximately 10 percent as compared to designs using more power-consuming isomers.

Panwar, Ramesh↗
NASA NTRS1993

Mixed voltage VLSI design

A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

Panwar, Ramesh↗
NASA NTRS1993

The Application of Microtechnology to Spacecraft On-Board Computing(abstract)

In this report, we will survey recent advances in chip packaging and stacking techniques that allow miniature computers to be developed for space applications. Several orders of magnitude reduction in mass, volume, and power consumption are possible using these techniques. Moreover, performance improvements can be achieved by increasing the scale of multiprocessing. Most importantly, long-term survivability can potentially be improved by increasing the level of redundancy and fault tolerance.

microtechnology computers multiprocessing packagin↗
NASA NTRS1992

Low energy CMOS for space applications

The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

Panwar, Ramesh↗