Engineering topics
Publications and source records attributed to Apelewicz, T..
The architecture of programmable processors is described, with particular reference to the design of a programmable delta-modulation decoder capable of receiving DM encoders employing different schemes. A switching receiver implementation, allowing communication between different DM algorithms, is designed and shown.
The implementation of a programmable microprocessor for real time speech processing is described. The design of a fast special-purpose computer operating at 150 nsec per instruction time reduces the problem of speech encoding and decoding to a software problem. Each instruction is a twelve-bit word, and the information conveyed by a word is explained. The microprocessor is controlled by two clocks - the A/D clock, or input sampling clock, which loads the digital input into the input register and presets the counter to a value set by the external switches; and the instruction clock, or system clock, which operates at 6 MHz. At this system clock rate and a sampling clock rate of 30 KHz, 200 instructions can be executed between samples, and for many speech encoding and decoding algorithms, 200 instructions are more than enough. The microcomputer is being used to test various delta modulator encoding algorithms.