Cd-excess and CdCl2 treatment effects on Sb-doped CdTe devices
Cd-excess and CdCl2 treatment effects on Sb-doped CdTe devices
Engineering topics
Publications and source records attributed to Arehart, Aaron.
Cd-excess and CdCl2 treatment effects on Sb-doped CdTe devices
The effect of high-temperature annealing (HTA) treatments and Cd-excess during the in-situ doping of CdSeTe:Sb is investigated. Optimized treatments eliminate the wurtzite phase from the as-deposited CdSeTe layer, while facilitating Se intermixing and grain size enhancement before CdCl2 treatment. The improved device stack quality results in a VOC improvement of 250 mV. VOC is further improved by tuning the Cd/Sb flux ratio during CdSeTe:Sb deposition. The lowest defect concentration is achieved at Cd/Sb of 1.4:1, which produced the best VOC CdSeTe:Sb cell with VOC = 849mV, despite a decreased carrier concentration due to the harsh CdCl2 treatment.
CdTe solar cells suffer from a non-ideal back contact which can strongly affect the equivalent circuit model and complicate capacitance measurements. Here, five different back contact materials are deposited on identical CdTe absorbers and their influence on capacitance measurements is characterized. A five-element equivalent circuit model is shown to represent a CdTe solar cell with a non-ideal back contact, and capacitance-frequency (C-f) measurements on each sample clearly show the influence of this contact. Capacitance-voltage (C-V) measurements on each sample show the influence of frequency on measured capacitance. In the AlGaOx/Au sample, temperature dependent C-fs show the back barrier height to be 240 meV, and ongoing measurements will give a comparison of back barrier heights for all samples. This study provides insight into the efficacy of various back contacts and highlights potential errors in the interpretation of capacitance measurements due to the presence of the back contact.
When this project began, CIGS and ACIGS solar cells were still well below the Shockley-Queisser efficiency limit for their bandgaps. Literature review from showed that JSC and FF were ~90% of the ideal values depending on the growth, but that VOC was only around 75% of the ideal value, which provided a clear objective to improve CIGS VOC. In polycrystalline CIGS, semiconductor defects (traps) have been shown by many studies to have detrimental impacts on device performance. Thus, the goal of this project was to investigate the sources and impacts of defects in CIGS, model their impact on device performance to predict efficiency improvements, and develop effective mitigation strategies to reduce the overall trap concentrations of these traps.