Engineering topics

Baker, Robert L.

Publications and source records attributed to Baker, Robert L..

4 records

NASA NTRS1993

Advanced Launch System Multi-Path Redundant Avionics Architecture Analysis and Characterization

The objective of the Multi-Path Redundant Avionics Suite (MPRAS) program is the development of a set of avionic architectural modules which will be applicable to the family of launch vehicles required to support the Advanced Launch System (ALS). To enable ALS cost/performance requirements to be met, the MPRAS must support autonomy, maintenance, and testability capabilities which exceed those present in conventional launch vehicles. The multi-path redundant or fault tolerance characteristics of the MPRAS are necessary to offset a reduction in avionics reliability due to the increased complexity needed to support these new cost reduction and performance capabilities and to meet avionics reliability requirements which will provide cost-effective reductions in overall ALS recurring costs. A complex, real-time distributed computing system is needed to meet the ALS avionics system requirements. General Dynamics, Boeing Aerospace, and C.S. Draper Laboratory have proposed system architectures as candidates for the ALS MPRAS. The purpose of this document is to report the results of independent performance and reliability characterization and assessment analyses of each proposed candidate architecture and qualitative assessments of testability, maintainability, and fault tolerance mechanisms. These independent analyses were conducted as part of the MPRAS Part 2 program and were carried under NASA Langley Research Contract NAS1-17964, Task Assignment 28.

Baker, Robert L.↗

NASA NTRS1992

Fly-By-Light/Power-By-Wire Requirements and Technology Workshop

The results of the Fly-By-Light/Power-By-Wire (FBL/PBW) Workshop held on March 17-19, 1992, at the NASA Langley Research Center are presented. The FBL/PBW program is a joint NASA LeRC/LaRC effort to develop the technology base for confident application of integrated FBL/PBW systems to transport aircraft. The objectives of the workshop were to ascertain the FBL/PBW program technical requirements and satisfy the requirements and needs from the industry viewpoint, provide a forum for presenting and documenting alternative technical approaches which satisfy the requirements, and assess the plan adequacy in accomplishing plan objectives, aims, and technology transfer. Areas addressed were: optical sensor systems, power-by-wire systems, FBL/PBW fault-tolerant architectures, electromagnetic environment assessment, and system integration and demonstration. The workshop consisted of an introductory meeting, a 'keynote' presentation, a series of individual panel sessions covering the above areas, with midway presentations by the panel chairpersons, followed by a final summarizing/integrating session by the individual panels, and a closing plenary session summarizing the results of the workshop.

Baker, Robert L.↗

NASA NTRS1991

Modeling methods for the design and evaluation of fault-tolerant systems

The authors describe an approach for using directed graph simulation models, behavioral simulation models, and semi-Markov analytic models to implement early- to mid-design analysis activities specified by the SDIO BM/C3 Processor and Algorithm Working Group. The use of the models was demonstrated for a mission scenario requiring parallel, reliable computations with a maximum probability of system failure between 10-4 and 10-2 over a 5-year-preengagement phase and between 10-7 and 10-5 over a half-hour engagement phase.

Scheper, Charlotte O.↗

NASA NTRS1988

A simulation-based fault injection experiment to evaluate self-test diagnostics for a fault-tolerant computer

The design and results of a fault injection experiment conducted in the Airlab facility at NASA-Langley using a logic network simulator are described. An attempt was made to determine the effectiveness of the diagnostic self-test sequences used to detect failures in the communicator/interstage (C/I) of a fault-tolerant processor (FTP). Identification of the undetected faults in the C/I Status Register logic resulted in changes in the diagnostic test sequences implemented for the FTP.

Baker, Robert L.↗