Bennett, Christopher H. (ORCID:000000026989292X)

DOE OSTI2021

Domain wall-magnetic tunnel junction spin–orbit torque devices and circuits for in-memory computing

There are pressing problems with traditional computing, especially for accomplishing data-intensive and real-time tasks, that motivate the development of in-memory computing devices to both store information and perform computation. Magnetic tunnel junction memory elements can be used for computation by manipulating a domain wall, a transition region between magnetic domains, but the experimental study of such devices has been limited by high current densities and low tunnel magnetoresistance. Here, we study prototypes of three-terminal domain wall-magnetic tunnel junction in-memory computing devices that can address data processing bottlenecks and resolve these challenges by using perpendicular magnetic anisotropy, spin–orbit torque switching, and an optimized lithography process to produce average device tunnel magnetoresistance TMR = 171% and average resistance-area product RA = 29 Ω μm2, close to the RA of the unpatterned film. Device initialization variation in switching voltage is shown to be curtailed to 7%–10% by controlling the domain wall initial position, which we show corresponds to 90%–96% accuracy in a domain wall-magnetic tunnel junction full adder simulation. Repeatability of writing and resetting the device is shown. A circuit shows an inverter operation between two devices, showing that a voltage window is large enough, compared to the variation noise, to repeatably operate a domain wall-magnetic tunnel junction circuit. These results make strides in using magnetic tunnel junctions and domain walls for in-memory and neuromorphic computing applications.

Alamdar, Mahshid (ORCID:0000000221732935)↗

DOE OSTI2020

Analog architectures for neural network acceleration based on non-volatile memory

Analog hardware accelerators, which perform computation within a dense memory array, have the potential to overcome the major bottlenecks faced by digital hardware for data-heavy workloads such as deep learning. Exploiting the intrinsic computational advantages of memory arrays, however, has proven to be challenging principally due to the overhead imposed by the peripheral circuitry and due to the non-ideal properties of memory devices that play the role of the synapse. We review the existing implementations of these accelerators for deep supervised learning, organizing our discussion around the different levels of the accelerator design hierarchy, with an emphasis on circuits and architecture. We explore and consolidate the various approaches that have been proposed to address the critical challenges faced by analog accelerators, for both neural network inference and training, and highlight the key design trade-offs underlying these techniques.

97 MATHEMATICS AND COMPUTING↗