Engineering topics
Publications and source records attributed to Benz, H. F..
A generic data system is briefly described. Its possible application to EOS instrument requirements is considered in the light of a survey of the NASA mission set to be flown over the time span of roughly 1990 to 1995.
The very high speed integrated circuit (VHSIC) program offers NASA and its contractors assured availability of military specification embedded computer components and integrated computer aided design/computer aided engineering and software development support that result in low system life costs for data management systems on the space station and the Earth Observatory Satellite. Viewgraphs given review progress in both the Department of Defense VHSIC program and the NASA VHSIC related insertion development of a general purpose processor are presented.
Imaging device uses surface-acoustic-wave (SAW) charge transfer for image readout. Spatial resolution of image changed electronically by changing frequency of applied signal. Surface acoustic waves create traveling longitudinal electric fields. These fields create potential wells that carry along stored charges. Charges injected into wells by photoelectric conversion when light strikes device.
The Information Adaptive System (IAS) is an element of the NASA End-to-End Data System (NEEDS) Phase II and is focused toward onboard image processing. The IAS is a data preprocessing system which is closely coupled to the sensor system. Some of the functions planned for the IAS include sensor response nonuniformity correction, geometric correction, data set selection, data formatting, packetization, and adaptive system control. The inclusion of these sensor data preprocessing functions onboard the spacecraft will significantly improve the extraction of information from the sensor data in a timely and cost effective manner, and provide the opportunity to design sensor systems which can be reconfigured in near real-time for optimum performance. The purpose of this paper is to present the preliminary design of the IAS and the plans for its development.
The paper describes an advanced technology development which utilizes a high speed analog/binary CCD correlator to perform the matrix multiplications necessary to implement onboard feature classification. The matrix manipulation module uses the maximum likelihood classification algorithm assuming a Gaussian probability density function. The module will process 16 element multispectral vectors at rates in excess of 500 thousand multispectral vector elements per second. System design considerations for the optimum use of this module are discussed, test results from initial device fabrication runs are presented, and the performance in typical processing applications is described
The potential uses of Charge Transfer Devices (CTDs) in pattern classification operations are explored. The needs for a hardware-based pattern classifier are established, and a matrix multiplication subsystem based upon a sum-of-products CTD is presented. Applications of the subsystem to the classification of multi-modal Gaussian distributions in general and to LANDSAT data processing in particular are discussed. Finally, the potential impact of this technology on satellite data processing methodologies is discussed.
The potential use of charge coupled device (CCD) programmable digital/analog correlators for multispectral data classification is discussed. CCD digital/analog correlator technology and the experimental evaluation of a 32-stage 4-bit test device are presented. The design of an IC for use in a multispectral classification system for 16 sensors and 8 bit accuracy is reviewed.
The potential uses of Charge Transfer Devices (CTDs) in pattern classification operations are explored. The needs for a hardware-based pattern classifier are established, and a matrix multiplication subsystem based upon a sum of products CTD is presented. An evaluation process for sum of products devices (particularly analog-analog correlators) is developed, and the feasibility of employing a particular device in a pattern classifier is determined. Finally, the possible impact of future trends in technology is considered.
In this paper discrete time analog signal processing applications of CCD's are discussed. The types of computations which can be performed in the CCD technology are discussed and compared with respect to their accuracy and required support hardware. The classification problem encountered in the reduction of multispectral data into features of terrestrial interest are decomposed into a CCD technology based hardware solution. The resulting system is readily implemented with existing and anticipated CCD devices. This system will be projected to spacecraft application.
Depletion-mode load devices can be integrated with DMOS transistors without any extra diffusions or ion implantation processing steps by judicious choice of the substrate crystal orientation and resistivity. For low voltage operation line-type 1, 1, 1 crystal orientation should be used. The line-type 1, 1, 1 crystal orientation also yields a higher transconductance for the DMOS transistor than the line-type 1, 0, 0 orientation. The geometry of the load device and the DMOS transistor can be made ratioless to conserve area. Self-aligned gates, hitherto considered incompatible with DMOS transistors, have been incorporated in the structure. The experimental DMOS inverters, using a conservative design, have achieved 4-ns propagation delay, 1.3-V operation, and 2-pJ propagation delay-power dissipation product.
Analog charge-coupled devices and sampled data filtering have developed into mature disciplines. Each discipline offers the other wide systems advantages where alone it would be impractical. This letter explores these advantages in a number of implementations against the scale of wide low-cost applications.
Explore the source record for details and available documents.
A linear voltage-tunable null device was predicted, fabricated, and tested. This filter is conceptually a distributed parameter RC representation of the channel of a MOSFET in a network configuration with a second MOSFET that is treated as a variable resistor. Classical transmission-line theory is used to predict a linear tuning curve with applied bias for the device. This concept was used to design a null device having a null that is linearly tunable in the range of 100 kHz. Such devices were fabricated and tested. Typical MOS processing steps were used and the resulting structures are compatible with the planar technology. The compatibility leads towards extension of this work to different frequency ranges for other specific applications.
Analysis, design, and fabrication of novel, variable frequency, distributed parameter filter