Criticality of Low-Energy Protons in Single-Event Effects Testing of Highly-Scaled Technologies
No abstract available
Engineering topics
Publications and source records attributed to Berg, M. D..
No abstract available
Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.
We report low-energy proton and alpha particle SEE data on a 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) that demonstrates the criticality of understanding and using low-energy protons for SEE testing of highly-scaled technologies
We investigate the use of commercial FPGA based evaluation boards for radiation testing DDR2 and DDR3 SDRAMs. We evaluate the resulting data quality and the tradeoffs involved in the use of these boards.
We present SEU test and analysis of the Microsemi ProASIC3 FPGA. SEU Probability models are incorporated for device evaluation. Included is a comparison to the RTAXS FPGA illustrating the effectiveness of the overall testing methodology.
A 1 GeV/u Fe-56 Ion beam allows for true 90 deg. tilt irradiations of various microelectronic components and reveals relevant upset trends for an abundant element at the galactic cosmic ray (GCR) flux-energy peak.
Initial total ionizing dose (TID) and single event heavy ion test results are presented for an unhardened commercial flash memory, fabricated with 63 nm technology. Results are that the parts survive to a TID of nearly 200 krad (SiO2), with a tractable soft error rate of about 10(exp -l2) errors/bit-day, for the Adams Ten Percent Worst Case Environment.
We present Single Event Effect (SEE) and Total Ionizing Dose (TID) data for 1 Gbit DDR SDRAMs (90 nm CMOS technology) as well as comparing this data with earlier technology nodes from the same manufacturer.