Engineering topics

Biedenbender, Michael D.

Publications and source records attributed to Biedenbender, Michael D..

3 records

NASA NTRS1991

Submicron gate InP power MISFET's with improved output power density at 18 and 20 GHz

The microwave characteristics are presented at 18 and 20 GHz of submicron gate indium phosphide (InP) metal-insulator-semiconductor field-effect transistors (MISFETs) for high output power density applications. InP power MISFET's were fabricated and the output power density was investigated as a function of drain-source spacing. The best output power density and gain were obtained for drain-source spacing of 3 micron. The output power density is 2.7 times greater than was previously measured for InP MISFET's at 18 and 20 GHz, and the power-added efficiency also increased.

Biedenbender, Michael D.↗

NASA NTRS1989

Ion-implanted high microwave power indium phosphide transistors

Encapsulated rapid thermal annealing (RTA) has been used in the fabrication of InP power MISFETs with ion-implanted source, drain, and active-channel regions. The MISFETs had a gate length of 1.4 microns. Six to ten gate fingers per device, with individual gate finger widths of 100 or 125 microns, were used to make MISFETs with total gate widths of 0.75, 0.8, or 1 mm. The source and drain contact regions and the channel region of the MISFETs were fabricated using Si implants in InP at energies from 60 to 360 keV with doses of (1-560) x 10 to the 12th/sq cm. The implants were activated using RTA at 700 C for 30 sec in N2 or H2 ambients using an Si3N4 encapsulant. The high-power high-efficiency MISFETs were characterized at 9.7 GHz, and the output microwave power density for the RTA conditions used was as high as 2.4 W/mm. For a 1-W input at 9.7 GHz gains up to 3.7 dB were observed, with an associated power-added efficiency of 29 percent and output power density 70 percent greater than that of GaAs MESFETs.

Biedenbender, Michael D.↗

NASA NTRS1987

Rapid thermal annealing of indium phosphide compound semiconductors

The rapid thermal annealing (RTA) of indium phosphide (InP) substrates using a proximity contact method and silicon nitride encapsulation is investigated. The surface conditions of the InP substrates following cleaning with procedures A and B are analyzed. Procedure A involves using an iodic acid solution to remove work-damage InP surface layers and B is a degasssing process and hydrofluoric acid solution for native oxide removal. AES, XPS, and SIMS data of the proximity contact and silicon nitride encapsulated annealed samples are examined. The data reveal that RTA using proximity contact with silicon wafers does not provide adequate protection; however, the InP sample is successfully annealed when protected by a silicon nitride encapsulant.

Biedenbender, Michael D.↗