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Blasche, P. R.

Publications and source records attributed to Blasche, P. R..

Analysis of first and second order binary quantized digital phase-locked loops for ideal and white Gaussian noise inputs

Specific configurations of first and second order all digital phase locked loops are analyzed for both ideal and additive white gaussian noise inputs. In addition, a design for a hardware digital phase locked loop capable of either first or second order operation is presented along with appropriate experimental data obtained from testing of the hardware loop. All parameters chosen for the analysis and the design of the digital phase locked loop are consistent with an application to an Omega navigation receiver although neither the analysis nor the design are limited to this application.

Blasche, P. R.↗

Analysis and design of a second-order digital phase-locked loop

A specific second-order digital phase-locked loop (DPLL) was modeled as a first-order Markov chain with alternatives. From the matrix of transition probabilities of the Markov chain, the steady-state phase error of the DPLL was determined. In a similar manner the loop's response was calculated for a fading input. Additionally, a hardware DPLL was constructed and tested to provide a comparison to the results obtained from the Markov chain model. In all cases tested, good agreement was found between the theoretical predictions and the experimental data.

Blasche, P. R.↗

Simulation of digital phase-locked loops

Simulation equations are developed for first and second order digital phase locked loops. Examples of loop simulation are given to determine loop performance with respect to several loop parameters.

Blasche, P. R.↗

Analysis of a first order phase locked loop in the presence of Gaussian noise

A first-order digital phase locked loop is analyzed by application of a Markov chain model. Steady state loop error probabilities, phase standard deviation, and mean loop transient times are determined for various input signal to noise ratios. Results for direct loop simulation are presented for comparison.

Blasche, P. R.↗