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Chau, Savio N.

Publications and source records attributed to Chau, Savio N..

14 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2011

NEXUS Scalable and Distributed Next-Generation Avionics Bus for Space Missions

A paper discusses NEXUS, a common, next-generation avionics interconnect that is transparently compatible with wired, fiber-optic, and RF physical layers; provides a flexible, scalable, packet switched topology; is fault-tolerant with sub-microsecond detection/recovery latency; has scalable bandwidth from 1 Kbps to 10 Gbps; has guaranteed real-time determinism with sub-microsecond latency/jitter; has built-in testability; features low power consumption (< 100 mW per Gbps); is lightweight with about a 5,000-logic-gate footprint; and is implemented in a small Bus Interface Unit (BIU) with reconfigurable back-end providing interface to legacy subsystems. NEXUS enhances a commercial interconnect standard, Serial RapidIO, to meet avionics interconnect requirements without breaking the standard. This unified interconnect technology can be used to meet performance, power, size, and reliability requirements of all ranges of equipment, sensors, and actuators at chip-to-chip, board-to-board, or box-to-box boundary. Early results from in-house modeling activity of Serial RapidIO using VisualSim indicate that the use of a switched, high-performance avionics network will provide a quantum leap in spacecraft onboard science and autonomy capability for science and exploration missions.

He, Yutao↗
NASA NTRS2011

Lunar Surface Systems Supportability Technology Development Roadmap

The Lunar Surface Systems Supportability Technology Development Roadmap is a guide for developing the technologies needed to enable the supportable, sustainable, and affordable exploration of the Moon and other destinations beyond Earth. Supportability is defined in terms of space maintenance, repair, and related logistics. This report considers the supportability lessons learned from NASA and the Department of Defense. Lunar Outpost supportability needs are summarized, and a supportability technology strategy is established to make the transition from high logistics dependence to logistics independence. This strategy will enable flight crews to act effectively to respond to problems and exploit opportunities in an environment of extreme resource scarcity and isolation. The supportability roadmap defines the general technology selection criteria. Technologies are organized into three categories: diagnostics, test, and verification; maintenance and repair; and scavenge and recycle. Furthermore, "embedded technologies" and "process technologies" are used to designate distinct technology types with different development cycles. The roadmap examines the current technology readiness level and lays out a four-phase incremental development schedule with selection decision gates. The supportability technology roadmap is intended to develop technologies with the widest possible capability and utility while minimizing the impact on crew time and training and remaining within the time and cost constraints of the program.

Oeftering, Richard C.↗
NASA NTRS2006

Catastrophic Fault Recovery with Self-Reconfigurable Chips

Mission critical systems typically employ multi-string redundancy to cope with possible hardware failure. Such systems are only as fault tolerant as there are many redundant strings. Once a particular critical component exhausts its redundant spares, the multi-string architecture cannot tolerate any further hardware failure. This paper aims at addressing such catastrophic faults through the use of 'Self-Reconfigurable Chips' as a last resort effort to 'repair' a faulty critical component.

fault tolerance↗
NASA NTRS2006

Catastrophic fault recovery with self-reconfigurable chips

Mission critical systems typically employ multi-string redundancy to cope with possible hardware failure. Such systems are only as fault tolerant as there are many redundant strings. Once a particular critical component exhausts its redundant spares, the multi-string architecture cannot tolerate any further hardware failure. This paper aims at addressing such catastrophic faults through the use of "Self-Reconfigurable Chips" as a last resort effort to "repair" a faulty critical component.

Chau, Savio N.↗
NASA NTRS2006

Deductive Glue Code Synthesis for Embedded Software Systems Based on Code Patterns

Automated code synthesis is a constructive process that can be used to generate programs from specifications. It can, thus, greatly reduce the software development cost and time. The use of formal code synthesis approach for software generation further increases the dependability of the system. Though code synthesis has many potential benefits, the synthesis techniques are still limited. Meanwhile, components are widely used in embedded system development. Applying code synthesis to component based software development (CBSD) process can greatly enhance the capability of code synthesis while reducing the component composition efforts. In this paper, we discuss the issues and techniques for applying deductive code synthesis techniques to CBSD. For deductive synthesis in CBSD, a rule base is the key for inferring appropriate component composition. We use the code patterns to guide the development of rules. Code patterns have been proposed to capture the typical usages of the components. Several general composition operations have been identified to facilitate systematic composition. We present the technique for rule development and automated generation of new patterns from existing code patterns. A case study of using this method in building a real-time control system is also presented.

automated code synthesis↗
NASA NTRS2006

Fault-tolerant communication channel structures

Systems and techniques for implementing fault-tolerant communication channels and features in communication systems. Selected commercial-off-the-shelf devices can be integrated in such systems to reduce the cost.

Alkalai, Leon↗
NASA NTRS2005

On Automating Failure Mode Analysis and Enforcing its Integrity

This paper reports our experience on the development of a design-for-safety (DFS) workbench called Risk Assessment and Management Environment (RAME) for microelectronic avionics systems. Our objective is to transform DFS practice from an ad-hoc, inefficient, error-prone approach to a stringent engineering process such that DFS can keep up with the rapidly growing complexity of avionics systems. In particular, RAME is built upon an information infrastructure that comprises a fault model, a knowledge base, and a failure reporting/tracking system. This infrastructure permits systematic learning from prior projects and enables the automation of failure modes, effects and criticality analysis (FMECA). Among other unique features, the most important advantage of RAME is its capability of directly accepting design source code in hardware description languages (HDLs) for automated failure mode analysis, which enables RAME to be compatible and to evolve with most electronic-computer-aided-design systems. Through an initial experimental evaluation of the RAME prototype, we show that our approach to FMECA automation improves failure mode analysis turn-around-time, completeness, and accuracy.

design for safety↗
NASA NTRS2002

Ultra-long-life spacecraft for long duration space exploration missions

The predominant failure mode in an ultra longlife system is the wear-out of components. In order to survive long duration missions, current fault tolerant design techniques would require excessive number of redundant components. This paper describes a more efficient fault tolerant avionics system architecture that requires much less redundant components. This architecture employs generic function blocks that can be programmed to replace a wide variety of components in-flight. Hence, each individual generic block is essentially equivalent to almost an entire redundant string of components in the conventional approach. In that way, the ultra long-life system can achieve much higher level of reliability while carrying much less components. On the other hand, due to the programmability of the generic redundant blocks, the physical location of a specific component might not be pre-determined. Therefore, wireless interconnection is employed to provide the necessary flexibility in connectivity. A testbed of this architecture is being developed at the Jet Propulsion Laboratory.

return missions↗
NASA NTRS2000

The Design of a Fault-Tolerant COTS-Based Bus Architecture for Space Applications

The high-performance, scalability and miniaturization requirements together with the power, mass and cost constraints mandate the use of commercial-off-the-shelf (COTS) components and standards in the X2000 avionics system architecture for deep-space missions. In this paper, we report our experiences and findings on the design of an IEEE 1394 compliant fault-tolerant COTS-based bus architecture. While the COTS standard IEEE 1394 adequately supports power management, high performance and scalability, its topological criteria impose restrictions on fault tolerance realization. To circumvent the difficulties, we derive a "stack-tree" topology that not only complies with the IEEE 1394 standard but also facilitates fault tolerance realization in a spaceborne system with limited dedicated resource redundancies. Moreover, by exploiting pertinent standard features of the 1394 interface which are not purposely designed for fault tolerance, we devise a comprehensive set of fault detection mechanisms to support the fault-tolerant bus architecture.

Chau, Savio N.↗
NASA NTRS2000

COTS-Based Fault Tolerance in Deep Space: Qualitative and Quantitative Analyses of a Bus Network Architecture

Using COTS products, standards and intellectual properties (IPs) for all the system and component interfaces is a crucial step toward significant reduction of both system cost and development cost as the COTS interfaces enable other COTS products and IPs to be readily accommodated by the target system architecture. With respect to the long-term survivable systems for deep-space missions, the major challenge for us is, under stringent power and mass constraints, to achieve ultra-high reliability of the system comprising COTS products and standards that are not developed for mission-critical applications. The spirit of our solution is to exploit the pertinent standard features of a COTS product to circumvent its shortcomings, though these standard features may not be originally designed for highly reliable systems. In this paper, we discuss our experiences and findings on the design of an IEEE 1394 compliant fault-tolerant COTS-based bus architecture. We first derive and qualitatively analyze a -'stacktree topology" that not only complies with IEEE 1394 but also enables the implementation of a fault-tolerant bus architecture without node redundancy. We then present a quantitative evaluation that demonstrates significant reliability improvement from the COTS-based fault tolerance.

Tai, Ann T.↗
NASA NTRS1999

The Design of a Fault-Tolerant COTS-Based Bus Architecture

In this paper, we report our experiences and findings on the design of a fault-tolerant bus architecture comprised of two COTS buses, the IEEE 1394 and the 12C. This fault-tolerant bus is the backbone system bus for the avionics architecture of the X2000 program at the Jet Propulsion Laboratory. COTS buses are attractive because of the availability of low cost commercial products. However, they are not specifically designed for highly reliable applications such as long-life deep-space missions. The X2000 design team has devised a multi-level fault tolerance approach to compensate for this shortcoming of COTS buses. First, the approach enhances the fault tolerance capabilities of the IEEE 1394 and 12 C buses by adding a layer of fault handling hardware and software. Second, algorithms are developed to enable the IEEE 1394 and the 12 C buses assist each other to isolate and recovery from faults. Third, the set of IEEE 1394 and 12 C buses is duplicated to further enhance system reliability. The X2000 design team has paid special attention to guarantee that all fault tolerance provisions will not cause the bus design to deviate from the commercial standard specifications. Otherwise, the economic attractiveness of using COTS will be diminished. The hardware and software design of the X2000 fault-tolerant bus are being implemented and flight hardware will be delivered to the ST4 and Europa Orbiter missions.

Chau, Savio N.↗
NASA NTRS1993

Self-checking on-line testable static RAM

This is a fault-tolerant random access memory for use in fault-tolerant computers. It comprises a plurality of memory chips each comprising a plurality of on-line testable and correctable memory cells disposed in rows and columns for holding individually addressable binary bits and provision for error detection incorporated into each memory cell for outputting an error signal whenever a transient error occurs therein. In one embodiment, each of the memory cells comprises a pair of static memory sub-cells for simultaneously receiving and holding a common binary data bit written to the memory cell and the error detection provision comprises comparator logic for continuously sensing and comparing the contents of the memory sub-cells to one another and for outputting the error signal whenever the contents do not match. In another embodiment, each of the memory cells comprises a static memory sub-cell and a dynamic memory sub-cell for simultaneously receiving and holding a common binary data bit written to the memory cell and the error detection provision comprises comparator logic for continuously sensing and comparing the contents of the static memory sub-cell to the dynamic memory sub-cell and for outputting the error signal whenever the contents do not match. Capability for correction of errors is also included.

Chau, Savio N.↗
NASA NTRS1989

On the feasibility of a spaceborne fault-tolerant hypercube

The feasibility of implementing a fault-tolerant hypercube architecture for space applications is discussed. Node-level architectures and designs are considered and a first-order reliability model is presented. It is shown how error recovery can be implemented using program rollback or roll-forward techniques. Shared memory augmentations to the message-passing structure can be used to get around the inefficiencies of multicomputers to provide efficient use of hardware to achieve the needed reliabilities while maintaining performance.

Rennels, David A.↗