Long-term stability-degradation analysis of DUNE SiPMs in Liquid Nitrogen
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47 OTHER INSTRUMENTATION↗
Engineering topics
Chen, Hucheng
Publications and source records attributed to Chen, Hucheng.
High-data throughput reconfigurable computing platform
A reconfigurable computing platform includes a reconfigurable computing device, electro-optical transceiver, and first voltage converter disposed on a multilayer board. The electro-optical transceiver converts an optical signal at least one of to and from an electrical signal, and the electrical signal is operatively coupled to the reconfigurable computing device. The electro-optical transceiver is disposed in proximity to the reconfigurable computing device, and the first voltage converter is operatively coupled to a common voltage distributed around a periphery of the multilayer board. The first voltage converter converts the common voltage to a first operating voltage, and the first voltage converter is disposed in proximity to the reconfigurable computing device. The first operating voltage is provided to the reconfigurable computing device as a first power source. A reconfigurable computing system includes a plurality of reconfigurable computing platforms operatively coupled together using an optical signal. A corresponding method of providing a reconfigurable computing platform is also disclosed.
Tang, Shaochun↗
High-bandwidth reconfigurable data acquisition card
A reconfigurable data acquisition card including at least one field programmable gate array (FPGA) and a configurable bus switch coupled with the FPGA. The bus switch forms at least first and second ports used by the FPGA, the bus switch being adaptable for insertion into a connection having a number of lanes at least equal to a combined number of lanes in the first and second ports. The data acquisition card further includes multiple optical transmitters and optical receivers. Each optical transmitter and optical receiver is coupled with a corresponding transceiver in the FPGA via at least one optical fiber having multiple communication links. Timing circuitry in the data acquisition card is coupled with clock generation and distribution circuitry in the FPGA and is configured to distribute clock and timing signals to detector front-ends with fixed latency and to synchronize input/output links with a system clock generated by the FPGA.
Chen, Kai↗
Cryogenic electronics for noble liquid neutrino detectors
In this paper we present the general features of cryogenic (or “cold”) electronics for noble liquid time projection chambers, with design principles and details for neutrino physics, a brief history of the technology and details of recent research and development that is driving the design of the detectors under construction. Finally, some comments on future R&D envisioned and the impact of this work on other fields is described. “Cold” in the context of this work applies to CMOS devices operated at 77 K and above, at liquids temperatures of LAr (89 K), LKr (125 K) and LXe (165 K), with most of the tests performed in, or at LN 2 (77 K). Additionally, the paper is concentrated on the design of cold electronics for large liquid argon TPCs, those that have been successfully operated, MicroBooNE and ProtoDUNE, and those designed or under construction, such as SBND and DUNE first and second 10 kton modules. The high performance achieved with MicroBooNE and ProtoDUNE – a high signal-to-noise ratio combined with high stability of response – is mainly due to the integral approach to design and construction of sensing electrodes with cold readout electronics in a modular approach with the cryostat signal feed-throughs incorporating warm interface electronics into a Faraday cage with the cryostat. The integral concept is described in some detail in this paper.
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
Readout of Large Capacitance SiPMs by Weak Coupling to Charge Sensitive Amplifier
Large area and large capacitance silicon photomultiplier (SiPM) arrays are employed to collect scintillation light in noble liquid time projection chambers (TPC) such as DarkSide, nEXO, MEGII, protoDUNE and DUNE. Light readout using ASICs designed for operation in noble liquids is a solution for large meter-scale photon detectors. However, conventional readout requires a high voltage decoupling capacitor larger than SiPM capacitance (in the range of tens of nF) to achieve full charge transfer to the preamplifier. Here, we demonstrate a readout concept by weakly coupling (via a capacitor lower by an order of magnitude than SiPM capacitance) to a charge sensitive amplifier, LArASIC in this case, without any loss in the signal to noise ratio (S/N). The single-photoelectron detection, signal-to-noise ratio, timing resolution, and coincidence detection are experimentally characterized.
47 OTHER INSTRUMENTATION↗
A Generic High Bandwidth Data Acquisition Card for Physics Experiments
In high energy physics and nuclear physics experiments particularly the ones based on particle accelerator, the data rate from the detector is usually in the order of Terabytes per second. This high throughput data from detector front-end electronics need to be transmitted to the back-end computing farm for high level event selection and building. A Data Acquisition (DAQ) system with features of high-density, scalable, easily upgradeable is crucial to simplify the readout architecture of whole experiment. This paper will introduce the design of a generic high bandwidth PCIe card which can be used as the important input output card in a scalable DAQ system. It can factorize front-end electronics from data handling, and reduce amount of custom hardware in favor of scalable detectorindependent commercial hardware and software. Besides the 48 channels of bidirectional high speed fiber optical links with frontends, it also supports to synchronize with the experiment timing system, and to fanout the clock and trigger information with a fixed latency to the front-end electronics.
72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
Design and Evaluation of the LAr Trigger Digitizer Board in the ATLAS Phase-I Upgrade
The Phase-I upgrade of the trigger readout electronics for the ATLAS Liquid Argon (LAr) calorimeters will be installed during the second long shutdown of the Large Hadron Collider (LHC) in 2019-2020 which will enable enhanced instantaneous luminosities during LHC Run 3 from 2021 through 2023. In this trigger upgrade, so-called supercells are introduced to provide higher granularity, higher resolution and longitudinal shower shape information from the LAr calorimeters to the Level-1 trigger processors. A new LAr Trigger Digitizer Board (LTDB) will process and digitize up to 320 channels of supercell signals, and transmit them via 40 fiber optical links to the back end where the data are further processed and transmitted to the trigger processors. Five pairs of bidirectional GBT links are used for slow control and monitoring between LTDB and the Front-End LInk eXchange (FELIX) in the ATLAS Trigger and Data Acquisition (TDAQ) system. Here, the LTDB also outputs 64 summed analog legacy signals to the current Tower Builder Board via a new baseplane. A test system for the production of 124 LTDBs has been developed, supporting configuration and calibration of all ASICs
72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
Development and data path integration test of the global Feature EXtractor for the ATLAS Level-1 calorimeter trigger system Phase-I upgrade
The global Feature Extractor (gFEX) is a component of the Phase-I upgrade of the Level-1 Calorimeter (L1Calo) trigger system for the ATLAS experiment at the Large Hadron Collider (LHC) at CERN. The gFEX is used to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W and Z bosons, top quarks, and exotic particles in real time at the 40 MHz LHC bunch crossing rate. Three prototypes were implemented and tested from 2014 to 2017. With the lessons learned from the prototypes, the final gFEX production board has been implemented at the end of 2017. The gFEX receives up to 300 fiber optical links from the calorimeter and transmits trigger data on 96 links to the ATLAS Level-1 Topological [1] (L1Topo) trigger at a rate of up to 12.8 Gb/s. There are also 24 electrical links on board for communication between two FPGAs running at speeds of up to 25.6 Gb/s. Here, the hardware functionality and performance of the production board have been evaluated. A data path integration test between the Liquid Argon Digital Processing Blade (LDPB) [2] and the Front End LInk eXchange (FELIX) [3] was performed successfully at CERN in 2018.
72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
Performance of CMOS pixel sensor prototypes in ams H35 and aH18 technology for the ATLAS ITk upgrade
Pixel sensors based on commercial high-voltage CMOS processes are an exciting technology that is considered as an option for the outer layer of the ATLAS inner tracker upgrade at the High Luminosity LHC. Here, charged particles are detected using deep n-wells as sensor diodes with the depleted region extending into the silicon bulk. Both analog and digital readout electronics can be added to achieve different levels of integration up to a fully monolithic sensor. Small scale prototypes using the ams CMOS technology have previously demonstrated that it can achieve the required radiation tolerance of 10(15) n(eq)/cm(2) and detection efficiencies above 99.5%. Recently, large area prototypes, comparable in size to a full sensor, have been produced that include most features required towards a final design: the H35demo prototype produced in ams H35 technology that supports both external and integrated readout and the monolithic ATLASPix1 pre-production design produced in ams aH18 technology. Both chips are based on large fill-factor pixel designs, but differ in readout structure. Performance results for H35DEMO with capacitively-coupled external readout and first results for the monolithic ATLASPix1 are shown.
ATLAS ITk upgrade↗
Cold electronics readout system for protoDUNE-SP LAr-TPC
The Single Phase (SP) TPC readout electronics are referred to as the Cold Electronics (CE) because they will operate in LAr, to minimize channel capacitance and noise by keeping the length of the connection between the anode wires and its corresponding electronics input to an absolute minimum. In this study, the CE system and preliminary results from the CE testing at warm and cold conditions after their installation on the protoDUNE-SP detector are presented.
72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗