Daniel J Zeleznikar | Search NASA

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NASA Lunar Exploration – Gateway’s Power and Propulsion Element Communications Links

As a key part of NASA’s Artemis program to return to the moon, the Lunar Gateway will provide a platform for staging lunar missions, for gaining experience in operations beyond earth orbit, and for creating sustainable infrastructure. Of specific interest, the Lunar Gateway will provide communications support to landers, orbiters, and surface systems, including in the South Polar Region where direct line of sight (LOS) to Earth is limited or non-existent. A foundational segment of the Gateway is the Power and Propulsion Element (PPE), which will carry: solar arrays to provide power to the Gateway; electric propulsion to maintain the Gateway in its operational orbit; and communication links between the Earth and Gateway, the Moon and Gateway, and relays from the Moon to the Earth. PPE Communication Links include an X-band link to Earth for Command, Ranging, and Telemetry (CR&T), which also carries low to medium rate data; a Ka-band Direct to Earth(DTE) link for high rate data transmissions; and a Ka-band Lunar link for high data rate connections to lunar systems. This paper describes the PPE communication links from a technical perspective. Other Gateway links supported by other modules are outside the scope of this paper.

ARTEMIS↗

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Field-Programmable Gate Array Implementation of a Single Photon-Counting Receive Modem

We present a field-programmable gate array (FPGA) implementation of a single photon-counting receive modem for a pulse position modulated signal. The modem is compliant with the Consultative Committee for Space Data Systems (CCSDS) High Photon Efficiency (HPE) Optical Communications Coding and Synchronization standard and is capable of a maximum data rate of 267 Mbps. The system is designed on a commercial off-the-shelf FPGA platform and utilizes superconducting nanowire single photon counting detectors, analog to digital converters (ADC s) to sample the detectors, and two FPGAs. Symbol timing recovery, photon counting, convolutional deinterleaving, and codeword synchronization areis performed in the first FPGA. The second FPGA performs iterative decoding on each codeword of the serially concatenated pulse position modulated (SCPPM) signal. A digital filter is included to compensate for timing jitter of the detector, and the decoder throughput can be modified adjusted through reconfigurable parallelization. The decoder also implements a resource-efficient, algorithmic polynomial interleaver and deinterleaver. Both FPGAs can be reconfigured to switch between pulse position modulation (PPM)-16 and PPM-32 with code rates 1/3, 1/2, and 2/3. In this paper, we describe the receiver architecture and FPGA implementation of the timing recovery loop and SCPPM decoder, FPGA utilization for the different modes, and receive modem characterization test results.

Field-programmable Gate Array↗