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Daud, T.

Publications and source records attributed to Daud, T..

At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2002

Rapid evolution of analog circuits configured on a field programmable transistor array

The purpose of this paper is to illustrate evolution of analog circuits on a stand-alone board-level evolvable system (SABLES). SABLES is part of an effort to achieve integrated evolvable systems. SABLES provides autonomous, fast (tens to hundreds of seconds), on-chip circuit evolution involving about 100,000 circuit evaluations. Its main components are a JPL Field Programmable Transistor Array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper details an example of evolution on SABLES and points out to certain transient and memory effects that affect the stability of solutions obtained reusing the same piece of hardware for rapid testing of individuals during evolution.

SABLES analog circuits field programmable transist↗
NASA NTRS2001

Evolvable Hardware for Extreme Environments: Hot or Cold

Temperature tolerant electronics and long life survivability are key capabilities required for future NASA/JPL missions. Current approaches to electronics for extreme environments focus on component level robustness and hardening. Compensation techniques, e.g., as offered by bias cancellation circuits, have also been employed. This paper presents a novel approach, based on evolvable hardware technology, which allows adaptive in situ circuit redesign/reconfiguration during the operation in the environment. This technology would complement material/device advancements and bring closer the success of missions in harsh environments. Additional information is contained in the original extended abstract.

Stoica, A.↗
NASA NTRS2000

Speed challenge: a case for hardware implementation in soft-computing

For over a decade, JPL has been actively involved in soft computing research on theory, architecture, applications, and electronics hardware. The driving force in all our research activities, in addition to the potential enabling technology promise, has been creation of a niche that imparts orders of magnitude speed advantage by implementation in parallel processing hardware with algorithms made especially suitable for hardware implementation. We review our work on neural networks, fuzzy logic, and evolvable hardware with selected application examples requiring real time response capabilities.

neural networks fuzzy logic evolvable hardware sof↗
NASA NTRS2000

On-chip learning of hyper-spectral data for real time target recognition

As the focus of our present paper, we have used the cascade error projection (CEP) learning algorithm (shown to be hardware-implementable) with on-chip learning (OCL) scheme to obtain three orders of magnitude speed-up in target recognition compared to software-based learning schemes. Thus, it is shown, real time learning as well as data processing for target recognition can be achieved.

on-chip learning Cascade Error Projection real tim↗
NASA NTRS1999

Reconfigurable Sensor Fusion Processing Hardware

The paper presents the concept and initial test from the hardware implementation of a low-power, high-speed reconfigurable sensor fusion processor.

Hardware implementation multisensor fusion data fu↗
NASA NTRS1999

ELIPS: Toward a Sensor Fusion Processor on a Chip

The paper presents the concept and initial tests from the hardware implementation of a low-power, high-speed reconfigurable sensor fusion processor. The Extended Logic Intelligent Processing System (ELIPS) processor is developed to seamlessly combine rule-based systems, fuzzy logic, and neural networks to achieve parallel fusion of sensor in compact low power VLSI.

sensor↗