Engineering topics
Publications and source records attributed to Deutsch, L. J..
A test using NASA's DSN to mimic the probe's signal was performed in 2000 and uncovered an anomaly that, unchecked, would result in nearly complete loss of the Huygens mission. This led to a suggested modification to the Cassini trajectory that will result in nearly complete data return for Huygens with minimal impact on Cassini.
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JPL's Interplanetary Network Directorate (IND) Technology Program was created to develop new and improved methods of communication, navigation, and operations.
Part of what makes small missions small is that they have less money. Executing missions at low cost implies extensive use of cost sharing with other missions or use of existing solutions. However, in order to create many small missions, new technology must be developed, applied, and assimilated. Luckily, there are methods for creating new technology and inserting it into faster-better-cheaper (FBC) missions.
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Part of what makes small missions small is that they have less money. Executing missions at low cost implies extensive use of cost sharing with other missions or use of existing solutions. Luckily, there are methods for creating new technology and inserting it into faster-better-cheaper missions.
The Galileo mission to Jupiter has implemented a wide range of telecommunication improvements in response to the loss of it's high gain antenna. Among the communications enhancements that have been made are the use of advanced compression techniques, packetized telemetry, new error correcting codes and algorithms, more efficient modulation, variable transmission data rates, routine ground antenna arraying (even between continents,) extremely sensitive ground receivers, and non-real-time automated data reconstruction. This telecommunications legacy of Galileo will aid in our abillity to conduct a meaningful exploration of the solar system, and beyond, at a reasonable cost.
On May 23, 1996, Galileo successfully switched to a new telecommunication mode with upgraded software on the spacecraft and comprehensively revised ground equipment. The new link offers multiple techniques (arraying, error-correcting coding, data compression, etc) to maximize the data return, while applying automation to minimize the complexity and cost of operations.
ave been developed to get as much data as possible from the Galileo spacecraft even without the high gain antenna. These methods include extensive data compression, a new packetized telemetry format, new error-correcting codes, new modulation, new ground receivers, and antenna arraying. (abstract only).
Channel and source coding theories are discussed. The following subject areas are covered: large constraint length convolutional codes (the Galileo code); decoder design (the big Viterbi decoder); Voyager's and Galileo's data compression scheme; current research in data compression for images; neural networks for soft decoding; neural networks for source decoding; finite-state codes; and fractals for data compression.
In this article, an overall plan for the development and demonstration of optical communications for deep-space applications is presented. The current state of the technology for optical communications is presented. Then, the development and demonstration plan is presented in two parts: the overall major systems activities, followed by the generic technology developments that will enable them. The plan covers the path from laboratory subsystems demonstrations out to a full-scale flight experiment system for the proposed Mars Communications Relay Orbiter mission.
Modification of decoding algorithms leads to simplified conceptual designs for time- and transform-domain Reed-Soloman (RS) decoders suitable for implementation as very-large-scale integrated (VLSI) circuits. New conceptual decoders determine simultaneously errata-locator and errata-evaluator polynomials as part of simplified scheme for corrections of errors and erasures in RS codes. Highly suitable for implementation in both VLSI circuitry and in software on general-purpose computer.
Size, weight, and susceptibility to burst errors reduced. Encoding system built on single very-large-scale integrated (VLSI) circuit chip produces (255,223) Reed-Solomon (RS) code with programmable interleaving up to depth of 5. (225,223) RS encoder includes new remainder-and-interleaver unit providing programmable interleaving of code words. Remainder-and-interleaver unit contains shift registers and modulo-2 adders. Signals on "turn" and "no-turn" lines control depth of interleaving. Based on E. R. Berlekamp's bit-serial multiplication algorithm for (225,223) RS encoder over Galois Field (2 to the 8th power).
Three different finite-field multipliers are presented: (1) a dual-basis multiplier due to Berlekamp; the Massey-Omura normal basis multiplier; and (3) the Scott-Tavares-Peppard standard basis multiplier. These algorithms are chosen because each has its own distinct features that apply most suitably in different areas. Finally, they are implemented on silicon chips with nitride metal oxide semiconductor technology so that the multiplier most desirable for VLSI implementation can readily be ascertained.
It is well known that the Euclidean algorithm or its equivalent, continued fractions, can be used to find the error locator polynomial needed to decode a Reed-Solomon (RS) code. It is shown that this algorithm can be used for both time and transform domain decoding by replacing its initial conditions with the Forney syndromes and the erasure locator polynomial. By this means both the errata locator polynomial and the errate evaluator polynomial can be obtained with the Euclidean algorithm. With these ideas, both time and transform domain Reed-Solomon decoders for correcting errors and erasures are simplified and compared. As a consequence, the architectures of Reed-Solomon decoders for correcting both errors and erasures can be made more modular, regular, simple, and naturally suitable for VLSI implementation.
The very large-scale integration (VLSI) architecture of a single chip (255, 223) Reed-Solomon decoder for decoding both errors and erasures is described. A decoding failure detection capability is also included in this system so that the decoder will recognize a failure to decode instead of introducing additional errors. This could happen whenever the received word contains too many errors and erasures for the code to correct. The number of transistors needed to implement this decoder is estimated at about 75,000 if the delay for received message is not included. This is in contrast to the older transform decoding algorithm which needs about 100,000 transistors. However, the transform decoder is simpler in architecture than the time decoder. It is therefore possible to implement a single chip (255, 223) Reed-Solomon decoder with today's VLSI technology. An implementation strategy for the decoder system is presented. This represents the first step in a plan to take advantage of advanced coding techniques to realize a 2.0 dB coding gain for future space missions.
A new very large scale integration (VLSI) design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous article is replaced by a time domain algorithm through a detailed comparison of their VLSI implementations. A new architecture that implements the time domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using a multiplexing technique, a new implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and significant reduction in silicon area.