Speed enhancement with soft computing hardware
We will review our work on electronic neural networks and evolvable hardware to bring out speed advantage.
soft computing neural networks evolvable hardware ↗
Engineering topics
Duong, T.
Publications and source records attributed to Duong, T..
Icy Satellites Impactor Probes for the Jovian Icy Moons Orbiter
We present a preliminary design and mission description for Icy Satellites Impactor Probes (IPS). This design addresses two of the scientific themes of this Icy Galilean Satellites Forum: Surface Chemistry and Geophysics, and Interior Structures. Impactor probes may also make significant contributions in the areas of surface geology and mineralogy.
Shirley, J. H.↗
Speed challenge: a case for hardware implementation in soft-computing
For over a decade, JPL has been actively involved in soft computing research on theory, architecture, applications, and electronics hardware. The driving force in all our research activities, in addition to the potential enabling technology promise, has been creation of a niche that imparts orders of magnitude speed advantage by implementation in parallel processing hardware with algorithms made especially suitable for hardware implementation. We review our work on neural networks, fuzzy logic, and evolvable hardware with selected application examples requiring real time response capabilities.
neural networks fuzzy logic evolvable hardware sof↗
Convergenece Analysis of Cascade Error Projection - An Efficient Learning Algorithm for Hardware Implementation
In this paper, we present a mathematical foundation, including a convergence analysis, for cascading architecture neural network.
Cascade Error Projection: Weight Quantization Hard↗
Reconfigurable Sensor Fusion Processing Hardware
The paper presents the concept and initial test from the hardware implementation of a low-power, high-speed reconfigurable sensor fusion processor.
Hardware implementation multisensor fusion data fu↗
Cascade Error Projection With Low Bit Weight Quantization for High Order Correlation Data
In this paper, we reinvestigate the solution for chaotic time series prediction problem using neural network approach. This study suggests that Cascade Error Projection (CEP) is an implementable learning technique for hardware consideration.
high↗
3-D VLSI Architecture Implementation for Data Fusion Problems
This paper gives an overview of hardware implementation techniques employed in solving real-time classification problems using Neural Network, Principle Component Analysis (PCA), and Independent Component Analysis (ICA) techniques.
3-D VLSI architecture data fusion neural networks↗
Cascade Error Projection - A Learning Algorithm for Hardware Implementation
In this paper, we workout a detailed mathematical analysis for a new learning algorithm termed Cascade Error Projection (CEP) and a general learning frame work.
cascading architecture hardware implementation pre↗
The Hardware Results of a 64 x 64 Analog Input Array for a 3-Dimensional Neural Network Processor
Algorithms for the solution of spatio-temporal recognition and classification problems are known to require intense image data computation.
3-dimensional artificial neural network (3DANN) Co↗
Winner/Loser-Take-All Circuits on SOI Technology for Neural Network Classification
High connectivity of artificial neural network chip-embodiments combined with currently emerging 3-dimensionally stacked multichip modules for real-time applications of target classification require a scrutiny for low power technology insertion.
neural↗
Fully Parallel ASIC Interface for a 3 Dimensional Processor for Image Convolution
Explore the source record for details and available documents.
CLIC die NPM cube fabricated die-jig digital circu↗
Low Temperature Performance of High-Speed Neural Network Circuits
Artificial neural networks, derived from their biological counterparts, offer a new and enabling computing paradigm specially suitable for such tasks as image and signal processing with feature classification/object recognition, global optimization, and adaptive control. When implemented in fully parallel electronic hardware, it offers orders of magnitude speed advantage. Basic building blocks of the new architecture are the processing elements called neurons implemented as nonlinear operational amplifiers with sigmoidal transfer function, interconnected through weighted connections called synapses implemented using circuitry for weight storage and multiply functions either in an analog, digital, or hybrid scheme.
artificial neural networks image processing signal↗
Mine Discrimination Using Multispectral Imagery With Feedforward Neural Networks
Simulated mine detection was performed on a polarimetric hyperspectral imaging dataset collected by using an acousto-optic tunable filter camera. A feedforward artificial neural network was programmed to recognize predefined spectral "templates." The simulation results are provided along with the preprocessing steps and window sizes leading to mine detection without false alarms.
polarimetric↗
Reconfigurable and Cascadable Analog Neuroprocessor
Artificial neural network paradigms have shown the capabilities of performing input-output.
Analog Neuroprocessor↗
Low Power Analog Neurosynapse Chips for a 3-D 'Sugarcube' Neuroprocessor
Object discrimination and patttern recognition are computationally intensive and for many defense and commercial applications, speed is of the essence.
3-D VLSI architecture reconfigurable multilayer pe↗
Learning to Classify Map Data with Cascaded VLSI Neural Network Building Block Chips
Paper maps are an important but unwieldy data format. To increase its utility, copious amounts of map data have been scanned into a digital map knowledge base. The next task in this knowledge base is to reduce this data to its underlying feature form suitable for analysis.
VLSI Neural Network Map Data↗
Learning and optimization with cascaded VLSI neural network building-block chips
To demonstrate the versatility of the building-block approach, two neural network applications were implemented on cascaded analog VLSI chips. Weights were implemented using 7-b multiplying digital-to-analog converter (MDAC) synapse circuits, with 31 x 32 and 32 x 32 synapses per chip. A novel learning algorithm compatible with analog VLSI was applied to the two-input parity problem. The algorithm combines dynamically evolving architecture with limited gradient-descent backpropagation for efficient and versatile supervised learning. To implement the learning algorithm in hardware, synapse circuits were paralleled for additional quantization levels. The hardware-in-the-loop learning system allocated 2-5 hidden neurons for parity problems. Also, a 7 x 7 assignment problem was mapped onto a cascaded 64-neuron fully connected feedback network. In 100 randomly selected problems, the network found optimal or good solutions in most cases, with settling times in the range of 7-100 microseconds.
Duong, T.↗