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Dupuis, Nicolas

Publications and source records attributed to Dupuis, Nicolas.

Configuration of an optical switch fabric using machine learning

An optical switch fabric comprises two or more optical switch elements. The optical switch elements are configured in a topology. A switch control has a plurality of bias control signals. The switch control can address one or more of the optical switch elements and can apply one of the bias control signals to bias of the addressed optical switch element to establish a switch setting. The topology and switch settings determine how each of one of the inputs is connected to each of one of the outputs of the optical switch fabric. The switch settings are determined by a machine learning process which includes a model creation. The model can be made to adapt dynamically during optical switch fabric operation.

Dupuis, Nicolas↗

Control of dual phase tuners

Techniques that facilitate control of dual phase tuners are provided. In one example, a system includes a first phase tuner and a second phase tuner. The first phase tuner is driven to a first phase bias that is different than a desired phase bias for an interferometer. The second phase tuner is driven to a second phase bias. A combination of the first phase bias and the second phase bias corresponds to the desired phase bias.

Lee, Benjamin Giles↗

An intra-node HPC network architecture with nanosecond-scale photonic switches

We propose a single-stage network architecture for intra-node connectivity that makes use of nanosecond-scale photonic switches. Although buffering at the switch points is of vital importance for complex multi-stage networks, this is not the case for smaller-scale single-stage networks where the end nodes are located only one hop apart. By limiting the buffering to the end points, the proposed architecture manages to minimize the required electro-optic and opto-electronic conversions, leading in this way to both low end-to-end latency and better energy efficiency. Combining these advantages with nanosecond-scale switching times can allow for high-throughput operation even for frequent switch reconfigurations. The performance of the proposed architecture is evaluated via discrete-event simulations for a wide range of synthetic-traffic cases. The simulation results show that high-throughput operation of ≥90% can be achieved even for small message sizes, i.e., 32 KB for all-to-all communication and 2 KB for uniform random traffic, at a data rate of 400 Gb/s and a switch reconfiguration time of ≤72 ns. Moreover, if 100-ns reconfiguration times are achievable as opposed to 150-ns, then for the all-to-all traffic case a 16% and 28% reduction in completion time can be achieved for message sizes of 8 KB and 1 KB, respectively. In a forthcoming era of optically interfaced processors and accelerators, nanosecond-scale photonic switches appear as a highly promising solution for keeping up with the intra-node bandwidth scaling due to their high-bandwidth, low-latency and fast-switching capabilities.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

A Dynamically-Reconfigurable Burst-Mode Link Using a Nanosecond Photonic Switch

Fast optical circuit switching has great potential to solve scaling issues with traditional packet-switch based networks and improve bandwidth and power efficiency in datacenter and high-performance computing applications. One difficultly in utilizing a fast optical switch is that the optical signal must be rapidly reacquired after each switching event so as to not significantly impact the overall throughput of the system. In this work we present a system-level integration of a nanosecond-scale $2 \times 2$ silicon photonic switch with a 25-Gbps burst-mode receiver that can lock in 31 ns. A novel FPGA-based control plane was used to generate test data, control the silicon photonic switch and burst-mode receiver, and measure bit errors at 12.5 and 20 Gbps. Error-free links (BER $< 10^{-12}$ ) with system-level reconfiguration times below 60 ns (at 20 Gbps) and 90 ns (at 12.5 Gbps) including bit- and frame-synchronization are demonstrated.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗