Engineering topics
Fay, Patrick
Publications and source records attributed to Fay, Patrick.
1.7-kV vertical GaN p-n diode with triple-zone graded junction termination extension formed by ion-implantation
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Edge termination in vertical GaN diodes: Electric field distribution probed by second harmonic generation
We characterized the electric field distribution of GaN-on-GaN p–n diodes with partially compensated ion-implanted edge termination (ET) using an electric field induced second harmonic generation technique (EFISHG). The distributed electric field from the anode to the outer edge of the ET demonstrates the effectiveness of the ET structure. However, EFISHG also shows that its effectiveness is strongly dependent on the acceptor charge distribution in the ET's partially compensated layer (PC). A generally lower amount of acceptor charge can be inferred from the measured electric field distribution resulting from excessive ion implantation energy or dose during ET fabrication and causing lower than optimal breakdown voltage. Localized field crowding can be observed when the remaining acceptors uncompensated by the implant in the PC layer are nonuniformly distributed around the periphery of the devices. Important information can be obtained from these direct electric field measurements and used for optimizing the device design and fabrication process.
Epitaxial Sc x Al 1- x N on GaN exhibits attractive high-K dielectric properties
Epitaxial Sc x Al 1- x N thin films of ~100 nm thickness grown on metal polar GaN substrates are found to exhibit significantly enhanced relative dielectric permittivity (ε r ) values relative to AlN. ε r values of ~17–21 for Sc mole fractions of 17%–25% ( x = 0.17–0.25) measured electrically by capacitance–voltage measurements indicate that Sc x Al 1- x N has the largest relative dielectric permittivity of any existing nitride material. Since epitaxial Sc x Al 1- x N layers deposited on GaN also exhibit large polarization discontinuity, the heterojunction can exploit the in situ high-K dielectric property to extend transistor operation for power electronics and high-speed microwave applications.
Ultrathin ferroic HfO 2 –ZrO 2 superlattice gate stack for advanced transistors
With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage. This led to a fundamental change in the gate stack in 2008, the incorporation of high-dielectric-constant HfO 2 , which remains the material of choice to date. Here we report HfO 2 –ZrO 2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric–antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal–oxide–semiconductor capacitors is equivalent to an effective SiO 2 thickness of approximately 6.5 ångströms. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO 2 -based high-dielectric-constant gate stacks without scavenging the interfacial SiO 2 , which has adverse effects on the electron transport and gate leakage current. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. This work demonstrates that ultrathin ferroic HfO 2 –ZrO 2 multilayers, stabilized with competing ferroelectric–antiferroelectric order in the two-nanometre-thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO 2 -based high-dielectric-constant materials.