Engineering topics

Feinberg, Ben

Publications and source records attributed to Feinberg, Ben.

4 records

DOE OSTI2024

Evaluation of Autonomous Vehicle Sensing and Compute Load on a Chassis Dynamometer

The sensing and compute load auxiliary energy consumption in autonomous vehicles may be significant due to the large number of sensors and the high compute load from sensor processing and route planning. To understand this issue, this study investigates the top-down energy usage of an electric 2015 Kia Soul fully instrumented with state sensors and a state-specific computer for path planning and sensor processing. A chassis dynamometer was then used to evaluate the cases of (1) no sensors or computation, (2) only sensors operating, and (3) sensors plus compute load. The vehicle was operated autonomously on the dynamometer using a PolySync drive-kit with drive-by-wire longitudinal control. The DynoJet model 224xLC was used to adapt the eddy current dynamometer's road load parameters to comply with an Environmental Protection Agency drive schedule and to evaluate performance against the Argonne National Laboratory Digital Dynamometer Dataset. On the UDDS-HWFET combined driving cycle, the stock battery's range was reduced by 5.6% for sensors alone and 12.2% for sensors and compute load. These results show that the added sensing and compute auxiliary load from automated and autonomous systems is significant and that research efforts need to be spent investigating new energy efficient systems.

Brown, Nicholas E.↗

DOE OSTI2021

Analysis and mitigation of parasitic resistance effects for analog in-memory neural network acceleration

To support the increasing demands for efficient deep neural network processing, accelerators based on analog in-memory computation of matrix multiplication have recently gained significant attention for reducing the energy of neural network inference. However, analog processing within memory arrays must contend with the issue of parasitic voltage drops across the metal interconnects, which distort the results of the computation and limit the array size. This work analyzes how parasitic resistance affects the end-to-end inference accuracy of state-of-the-art convolutional neural networks, and comprehensively studies how various design decisions at the device, circuit, architecture, and algorithm levels affect the system's sensitivity to parasitic resistance effects. Here, a set of guidelines are provided for how to design analog accelerator hardware that is intrinsically robust to parasitic resistance, without any explicit compensation or re-training of the network parameters.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2021

Multiscale System Modeling of Single-Event-Induced Faults in Advanced Node Processors

Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an integrated processor’s scope makes physically correct modeling computationally intractable. Without useful models, presilicon evaluation of fault-tolerance approaches becomes impossible. To incorporate accurate transistor-level effects at a system scope, we present a multiscale simulation framework. Charge collection at the 1) device level determines 2) circuit-level transient duration and state-upset likelihood. Circuit effects, in turn, impact 3) register-transfer-level architecture-state corruption visible at 4) the system level. Furthermore, the physically accurate effects of SEEs in large-scale systems, executed on a high-performance computing (HPC) simulator, could be used to drive cross-layer radiation hardening by design. We demonstrate the capabilities of this model with two case studies. First, we determine a D flip-flop’s sensitivity at the transistor level on 14-nm FinFet technology, validating the model against published cross sections. Second, we track and estimate faults in a microprocessor without interlocked pipelined stages (MIPS) processor for Adams 90% worst case environment in an isotropic space environment.

42 ENGINEERING↗

DOE OSTI2020

Adapting In Situ Accelerators for Sparsity With Granular Matrix Reordering

Neural network (NN) inference is an essential part of modern systems and is found at the heart of numerous applications ranging from image recognition to natural language processing. In situ NN accelerators can efficiently perform NN inference using resistive crossbars, which makes them a promising solution to the data movement challenges faced by conventional architectures. Although such accelerators demonstrate significant potential for dense NNs, they often do not benefit from sparse NNs, which contain relatively few non-zero weights. Processing sparse NNs on in situ accelerators results in wasted energy to charge the entire crossbar where most elements are zeros. To address this limitation, this paper proposes Granular Matrix Reordering (GMR): a preprocessing technique that enables an energy-efficient computation of sparse NNs on in situ accelerators. GMR reorders the rows and columns of sparse weight matrices to maximize the crossbars' utilization and minimize the total number of crossbars needed to be charged. The reordering process does not rely on sparsity patterns and incurs no accuracy loss. Finally, GMR achieves an average of 28% and up to 34% reduction in energy consumption over seven pruned NNs across four different pruning methods and network architectures.

97 MATHEMATICS AND COMPUTING↗