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Garcia, Ernest J.

Publications and source records attributed to Garcia, Ernest J..

6 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2019

Coupled memristor devices to enable feedback control and sensing of micro/nanoelectromechanical actuator and sensors

A MEMS apparatus with dynamic displacement control includes a MEMS parallel plate capacitor integrated with one or more memristors in a series configuration wherein a displacement is observable as a function of memristance, such that an upper electrode position is capable of being interpreted in a form of a resistance rather than a capacitance. The current is limited by said MEMS parallel plate capacitor restricting a change in the resistance of the memristor(s). The memristor(s) can be employed in some embodiments a sensor element to improve a MEMS operation range.

42 ENGINEERING↗
DOE OSTI2015

MEMS closed-loop control incorporating a memristor as feedback sensing element

In this work the integration of a memristor with a MEMS parallel plate capacitor coupled by an amplification stage is simulated. It is shown that the MEMS upper plate position can be controlled up to 95% of the total gap. Due to its common operation principle, the change in the MEMS plate position can be interpreted by the change in the memristor resistance, or memristance. A memristance modulation of ~1 KΩ was observed. A polynomial expression representing the MEMS upper plate displacement as a function of the memristance is presented. Thereafter a simple design for a voltage closed-loop control is presented showing that the MEMS upper plate can be stabilized up to 95% of the total gap using the memristor as a feedback sensing element. As a result, the memristor can play important dual roles in overcoming the limited operation range of MEMS parallel plate capacitors and in simplifying read-out circuits of those devices by representing the motion of the upper plate in the form of resistance change instead of capacitance change.

42 ENGINEERING↗
DOE OSTI2013

Die singulation method

A method is disclosed for singulating die from a semiconductor substrate (e.g. a semiconductor-on-insulator substrate or a bulk silicon substrate) containing an oxide layer (e.g. silicon dioxide or a silicate glass) and one or more semiconductor layers (e.g. monocrystalline or polycrystalline silicon) located above the oxide layer. The method etches trenches through the substrate and through each semiconductor layer about the die being singulated, with the trenches being offset from each other around at least a part of the die so that the oxide layer between the trenches holds the substrate and die together. The trenches can be anisotropically etched using a Deep Reactive Ion Etching (DRIE) process. After the trenches are etched, the oxide layer between the trenches can be etched away with an HF etchant to singulate the die. A release fixture can be located near one side of the substrate to receive the singulated die.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗