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Gary W Hunter

Publications and source records attributed to Gary W Hunter.

At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2023

Venus Surface Environmental Chamber Test of SiC JFET-R Multi-Chip Circuit Board

This poster describes a first attempt to demonstrate a multi-chip prototype lander control and sensor signal digitization electronics circuit board comprised of ten NASA Glenn IC Generation 11 SiC JFET-R IC chips in 460 °C, 9.4 MPa harsh Venus surface conditions. The lander circuit ceased electrical operation prematurely at 107 °C as the Venus chamber heated up. Optical and SEM post-test inspections indicate fatal dielectric cracks occurred on only one of the ten SiC chips.

silicon carbide↗
NASA NTRS2020

Development of a Venus Surface Wind Sensor Based on a Miniature Drag-Force Anemometer

To better understand the atmospheric structure and dynamics on the Venus surface and provide input to climate models, there is a need to measure the wind velocity and direction on the surface and track changes over extended periods. A wind sensor based on a miniature drag-force anemometer is being developed to meet the challenges for wind measurements and operational requirements on the surface of Venus. The sensor materials are chosen to enhance durability and prevent reactivity with the Venus surface atmosphere. Advantages of this approach include that it is independent on variable heat transfer, has been matured in other harsh environment applications,and has a low mass and power requirement. This report describes demonstration of this miniature drag-force anemometer integrated with high temperature electronics in simulated Venus surface environment. Prototype drag-force anemometers were demonstrated integrated with an operational amplifier recording transient effects in a simulated Venus surface environment. For multidirectional wind monitoring, the sensors are small enough to be deployed orthogonally as a three-dimensional array on a small arm or mast

wind measurement↗
NASA NTRS2020

High Temperature Electronics for Venus Surface Applications: A Summary of Recent Technical Advances

This white paper has a technical focus meant to provide background to those unfamiliar with the challenges of high temperature electronics, and an understanding of why new surface mission concepts are now viable for Venus and other applications. It describes that, for the first time, high temperature electronics have been developed to enable a paradigm change in extended duration Venus surface exploration. This white paper concentrates on the advances made in Silicon Carbide (SiC) integrated circuit (IC) electronics that have matured to a state where a simple long-life scientific probe is feasible for Venus surface operations. These electronics have been demonstrated for more than a year at 500˚C, 60 days in high-fidelity simulated Venus surface conditions chamber, and have been integrated and demonstrated with prototype long-lived scientific observation sensor technology. Continued maturation of these needed high temperature electronics and sensors is ongoing in the Long-Lived In-Situ Solar System Explorer (LLISSE) project to provide an operational system including sensor control and operation, signal processing, power management, and communications in the early part of the 2020’s. A key focus of this work includes increasing the complexity and decreasing the power consumption of the ICs which will pave the way to enhanced capabilities, such as long-duration Venus seismic measurements. Other IC development efforts include high temperature memory, terrestrial based characterization of volcanic magma, and development of a simple microprocessor. This electronics has also shown to have exceptionally high radiation tolerance, and thus have relevance for a broad range of solar system exploration. Although presently at the level of complexity of 1970-1980 silicon-based electronics, such electronics can enable breakthroughs in Venus planetary exploration akin to 1970s-launched planetary exploration successes (such as Viking and Voyager).

High temperature Electronics↗
NASA NTRS2020

Compass Final Report: Venus Bridge Orbiter and Surface Study (V-BOSS)

The Venus Bridge Orbiter and Surface Study (V-BOSS) Compass concurrent engineering design team study shows that new, high-priority Venus science can be achieved using a linked Orbiter + Surface Element (Lander) mission concept within a $200M cost cap with assumptions. This is feasible through optimizing investment in early technologies and platforms, such as the Long-Lived In-Situ Solar System Explorer (LLISSE), leveraging known and flight-ready technology, and the overall use of simple, small, robust systems in innovative approaches to Venus exploration. This architecture allows a range of science investigations through modification of Orbiter-Lander platforms in this study through choice of other instruments (often sensors), science themes, or operational modes. In particular, a fundamental strength of this approach is to provide science not available in other ways by using simplified architectures including rugged systems operable in-situ on the Venus surface. Such investigations would be pathfinders for more complex, and more expensive, future missions. Additionally, the results of this study can be used to further champion the need, value and return of early investment technology programs for the hard problem of in-situ investigations at Venus.

Venus Bridge↗
NASA NTRS2018

Operational Testing of 4H-SiC JFET ICs for 60 Days Directly Exposed to Venus Surface Atmospheric Conditions

Prolonged Venus surface missions (lasting months instead of hours) have proven infeasible to date in the absence of a complete suite of electronics able to function for such durations without protection from the planet’s extreme conditions of ~460 °C, ~9.3 MPa (~ 92 Earth atmospheres) chemically reactive environment. Here we report testing data from a successful two-month (60-day) operational demonstration of two 175-transistor 4H-SiC junction field effect transistor (JFET) semiconductor integrated circuits (ICs) directly exposed (no cooling and no protective chip packaging) to a high-fidelity physical and chemical reproduction of Venus surface atmospheric conditions in a test chamber. These results extend the longest reported duration of electronics operation in Venus surface atmospheric conditions almost 3-fold and were accomplished using prototype SiC JFET chips of more than 7-fold increased complexity. The demonstrated advancement marks a significant step towards realization of electronics with sufficient complexity and durability for implementing robotic landers capable of returning months of scientific data from the surface of Venus.

Integrated Circuit↗
NASA NTRSDate not supplied

Smart Sensor Systems for Human Health and Environmental Applications

Sensors and sensor systems are central to providing improved awareness of an individual's health state and surroundings. This presentation describes efforts to develop Smart Sensor Systems for a range of health and safety applications moving towards distributed intelligence. This includes efforts to develop a human health breath monitoring system using this microsensor Smart Sensor System approach. The same core technology can be used for a range of applications related to improved human health and environmental monitoring. Other examples of human health relevant technology development will also be given.

Smart Sensors Health↗
NASA NTRSDate not supplied

A 96% Alumina based Packaging System for 500°C Test of SiC Integrated Circuits

With the development of silicon carbide (SiC) sensors and electronic devices for operation at 500°C, compatible packaging technologies are needed for long term high temperature test and deployment of these sensors and electronic devices. 96% Al2O3ceramic is an excellent electrically insulating material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. This paper presents a packaging system for low power integrated circuits including a prototype 8-I/O chip-level package and printed circuit board (PCB) based on 96% Al2O3ceramic substrates and Au thick-film metallization for 500°C applications. The details related to designs of packages and PCBs, packaging materials, and specific packaging step recipes including wire -bonding and die-attach, are presented. Some test results of this prototype packaging approach applied to SiC integrated circuits at 500°C are reviewed.

High Temperature, Packaging, Alumina, Thick Film↗
NASA NTRSDate not supplied

An Overview of High Temperature Technologies for Venus Surface Applications

A brief overview is given on a range of high temperature technologies related to possible extended duration Venus surface exploration. This overview includes the Venus technology plan and Surface Platform study, and development in projects such as the Long Lived Solar System Explorer, and High Operating Temperature Technology 2016 and 2021.

Venus surface exploration high temperature technol↗
NASA NTRSDate not supplied

Nanostructured Material Sensor Processing Using Microfabrication Technology

This presentation discusses the fabrication of microsensors based based on nanomaterials and microfabrication technology. In particular, is it shown that nanostructured materials can be incorporated into standard micro fabrication techniques yielding improved alignment and electrical contact in a microsensor platform. A nano templating technique is also shown which provides sensor structures with unique properties.

chemical sensors nanostructures nanomaterials micr↗
NASA NTRSDate not supplied

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

A prototype high temperature co-fired ceramic (HTCC) alumina packaging system composed of a 32-I/Os package and a compatible circuit board was previously developed and demonstrated for long term operation in 500 °C environments. The electrical / dielectric parasitic parameters of that chip level package were characterized and reported. This co-fired packaging system with platinum (Pt) conductor has successfully facilitated tests of silicon carbide (SiC) analog and digital integrated circuits (ICs) developed at NASA GRC at 500°C for up to 10,000 hours in ambient oven environment and 60 earth days in Venus surface environment with simulated temperature, pressure, and chemical constituents. Based on these previous results, this paper introduces new designs of Pt-HTCC packages with 16, 24, and 44 I/Os for packaging a new generation SiC ICs with 8, 24, 56, 62, and 72 I/Os to be tested in high temperature harsh environments. The package with 44 I/Os is specifically designed for the new SiC ICs with 56, 62, and 72-I/Os and electrical connection needs, the power pads of this package are consolidated, and an array of I/O pads distributed on separated vertical levels (inside the package) is used to control the overall package dimensions and mitigate the parasitic effects at high temperatures. This paper will present the detailed design of these chip-level packages and results of electrical and dielectric characterization of these newly fabricated chip-level Pt-HTCC packages.

High temperature↗
NASA NTRSDate not supplied

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

A prototype high temperature co-fired ceramic (HTCC) alumina packaging system composed of a 32-I/Os package and a compatible circuit board was previously developed and demonstrated for long term operation in 500 °C environments. The electrical / dielectric parasitic parameters of that chip level package were characterized and reported. This co-fired packaging system with platinum (Pt) conductor has successfully facilitated tests of silicon carbide (SiC) analog and digital integrated circuits (ICs) developed at NASA GRC at 500°C for up to 10,000 hours in ambient oven environment and 60 earth days in Venus surface environment with simulated temperature, pressure, and chemical constituents. Based on these previous results, this paper introduces new designs of Pt-HTCC packages with 16, 24, and 44 I/Os for packaging a new generation SiC ICs with 8, 24, 56, 62, and 72 I/Os to be tested in high temperature harsh environments. The package with 44 I/Os is specifically designed for the new SiC ICs with 56, 62, and 72-I/Os and electrical connection needs, the power pads of this package are consolidated, and an array of I/O pads distributed on separated vertical levels (inside the package) is used to control the overall package dimensions and mitigate the parasitic effects at high temperatures. This paper will present the detailed design of these chip-level packages and results of electrical and dielectric characterization of these newly fabricated chip-level Pt-HTCC packages.

High temperature↗
NASA NTRSDate not supplied

An Overview of High Temperature Venus Surface Lander and Smart Systems Technologies

The extreme surface conditions of Venus, including high temperature/pressure and reactive chemistry, have previously limited the lifetime of surface missions to ~2 hours. Recent advances in high temperature technologies suggest the possibility of extended duration missions on the Venus surface. This presentation gives a brief overview of a range of high temperature technologies to enable a possible extended duration Venus surface mission, as well as an overview of the motivation and challenges of Venus surface exploration. The technology development under the Long-Lived In Situ Solar System Explorer (LLISSE) project is aimed towards developing a full lander system operational for 60 days on the Venus surface and included a power source, electronics, communications, sensors, and the structure, each at a different level of maturity. This presentation briefly describes these and other lander system technologies, their relative level of maturity, and planned future development for Venus surface exploration. Relevance to Aeronautic applications is briefly discussed.

Venus high temperature technologies vehicle health↗