Engineering topics
Publications and source records attributed to Gassaway, J. D..
Report describes one-year research effort in VLSL fabrication. Four activities are described: theoretical study of two-dimensional diffusion in SOS (silicon-on-sapphire); setup of sputtering system, furnaces, and photolithography equipment; experiments on double layer metal; and investigation of two-dimensional modeling of MOSFET's (metal-oxide-semiconductor field-effect transistors).
Quarterly report describes progress in three programs: dc sputtering machine for aluminum and aluminum alloys; two dimensional computer modeling of MOS transistors; and development of computer techniques for calculating redistribution diffusion of dopants in silicon on sapphire films.
Simulations of various phosphorus and boron diffusions in SOS were completed and a sputtering system, furnaces, and photolithography related equipment were set up. Double layer metal experiments initially utilized wet chemistry techniques. By incorporating ultrasonic etching of the vias, premetal cleaning a modified buffered HF, phosphorus doped vapox, and extended sintering, yields of 98% were obtained using the standard test pattern. A two dimensional modeling program was written for simulating short channel MOSFETs with nonuniform substrate doping. A key simplifying assumption used is that the majority carriers can be represented by a sheet charge at the silicon dioxide silicon interface. Although the program is incomplete, the two dimensional Poisson equation for the potential distribution was achieved. The status of other Z-D MOSFET simulation programs is summarized.
The use of dry processing and alternate dielectrics for processing wafers is reported. A two dimensional modeling program was written for the simulation of short channel MOSFETs with nonuniform substrate doping. A key simplifying assumption used is that the majority carriers can be represented by a sheet charge at the silicon dioxide-silicon interface. In solving current continuity equation, the program does not converge. However, solving the two dimensional Poisson equation for the potential distribution was achieved. The status of other 2D MOSFET simulation programs are summarized.
Furnaces and photolithography related equipment were applied to experiments on double layer metal. The double layer metal activity emphasized wet chemistry techniques. By incorporating the following techniques: (1) ultrasonic etching of the vias; (2) premetal clean using a modified buffered hydrogen fluoride; (3) phosphorus doped vapor; and (4) extended sintering, yields of 98 percent were obtained using the standard test pattern. The two dimensional modeling problems have stemmed from, alternately, instability and too much computation time to achieve convergence.
A system was developed for depositing aluminum and aluminum alloys by the D.C. sputtering technique. This system which was designed for a high level of cleanliness and ion monitoring the deposition parameters during film preparation is ready for studying the deposition and annealing parameters upon double level metal preparation. The finite element method was studied for use in the computer modeling of two dimensional MOS transistor structures. An algorithm was developed for implementing a computer study which is based upon the finite difference method. The program was modified and used to calculate redistribution data for boron and phosphorous which had been predeposited by ion implantation with range and straggle conditions typical of those used at MSFC. Data were generated for 111 oriented SOS films with redistribution in N2, dry O2 and steam ambients. Data are given showing both two dimensional effects and the evolution of the junction depth, sheet resistance and integrated dose with redistribution time.
A sputtering system was developed to deposit aluminum and aluminum alloys by the dc sputtering technique. This system is designed for a high level of cleanliness and for monitoring the deposition parameters during film preparation. This system is now ready for studying the deposition and annealing parameters upon double-level metal preparation. A technique recently applied for semiconductor analysis, the finite element method, was studied for use in the computer modeling of two dimensional MOS transistor structures. It was concluded that the method has not been sufficiently well developed for confident use at this time. An algorithm was developed for confident use at this time. An algorithm was developed for implementing a computer study which is based upon the finite difference method. The program which was developed was modified and used to calculate redistribution data for boron and phosphorous which had been predeposited by ion implantation with range and straggle conditions. Data were generated for 111 oriented SOS films with redistribution in N2, dry O2 and steam ambients.
Package of three computer programs performs two-dimensional electrostatic analysis to determine efficiency of charge transfer. One program can be used to analyze three-electrode charge-coupled device input/output gates, and other two programs can be used to analyze two-phase structures containing two or four electrodes with periodic boundary conditions.
A 4-phase, 49 1/2 bit CCD shift register was designed and fabricated using two levels of aluminum metallization with anodic Al2O3 insulation separating the layers. Test circuitry was also designed and constructed. A numerical analysis of an MOS-RC transmission line was made and results are given to characterize performance for various conductivities. The electrical design of the CCD included a low-noise dual-gate input and a balanced floating diffusion output circuit. Metallization was accomplished both by low voltage DC sputtering and thermal evaporation. The audization was according to published procedures using a buffered tartaric acid bath. Approximately 20 wafers were processed with 50 complete chips per wafer. All devices failed by shorting between the metal levels at some point. Experimental procedures eliminated temperature effects from sintering and drying, anodic oxide thickness, edge effects, photoresist stripping procedures, and metallization techniques as the primary causes of failure. It was believed from a study of SEM images that protuberances (hillocks) grow up from the first level metal through the oxide either causing a direct short or producing a weak, highly stressed insulation point which fails at low voltage. The cause of these hillocks is unknown; however, they have been observed to grow during temperature excursions to 470 C.
The fundamental problems encountered in designing, fabricating, and applying CCD's are reviewed. Investigations are described and results and conclusions are given for the following: (1) the development of design analyses employing computer aided techniques and their application to the design of a grapped structure; (2) the role of CCD's in applications to electronic functions, in particular, signal processing; (3) extending the CCD to silicon films on sapphire (SOS); and (4) all aluminum transfer structure with low noise input-output circuits. Related work on CCD imaging devices is summarized.
Two approaches have been taken to study CCD's and some of their fundamental limitations. First a numerical analysis approach has been developed to solve the coupled transport and Poisson's equation for a thorough analysis of charge transfer in a CCD structure. The approach is formulated by treating the minority carriers as a surface distribution at the Si-SiO2 interface and setting up coupled difference equations for the charge and the potential. The SOR method is proposed for solving the two dimensional Poisson's equation for the potential. Methods are suggested for handling the discontinuities to improve convergence. Second, CCD shift registers were fabricated with parameters which should allow complete charge transfer independent of the transfer electrode gap width. A test instrument was designed and constructed which can be used to test this, or any similar, three phase CCD shift register.
An analysis is presented which is based upon a numerical solution of Gauss's law for the multiple dielectric semiconductor and electrode structure. The formulation resulted in a large set of equations, usually nonlinear, which were solved by an iterative scheme based upon the Gauss-Seidel method employing a relaxation parameter. Proper consideration of the nonlinearity of the space-charge in the semiconductor allowed convergent solutions which can give reasonable approximations to the channel potential profiles though not as good for estimating the space charge itself. The results of this work, which are three computer programs, are listed. None of the programs give the electric field explicitly as output data. However, when this information is desired, the programs can be expanded to include field estimations based on a polynominal fit to the potential field, or they may serve as subprograms for main programs dealing with general aspects of charge transfer.
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The development of the DELTIC DFPCC serial mode signal processor is discussed. The processor is designed to detect in the presence of background noise a signal coded into the zero crossings of the waveform. The unique features of the DELTIC DFPCC include versatility in handling a variety of signals and relative simplicity in implementation. A theoretical performance model is presented which predicts the expected value of the output signal as a function of the input signal to noise ratio. Experimental results obtained with the prototype system, which was breadboarded with LSI, MSI and SSI components, are given. The device was compared with other LSI schemes for signal processing and it was concluded that the DELTIC DFPCC is simpler and in some cases more versatile than other systems. With established LSI technology, low frequency systems applicable to sonar and similar problems are feasible.
The computer simulation of the electrical behavior of a Gate-Controlled Diode (GCD) fabricated in Silicon-On-Sapphire (SOS) was described. A procedure for determining lifetime profiles from capacitance and reverse current measurements on the GCD was established. Chapter 1 discusses the SOS structure and points out the need of lifetime profiles to assist in device design for GCD's and bipolar transistors. Chapter 2 presents the one-dimensional analytical formula for electrostatic analysis of the SOS-GCD which are useful for data interpretation and setting boundary conditions on a simplified two-dimensional analysis. Chapter 3 gives the results of a two-dimensional analysis which treats the field as one-dimensional until the silicon film is depleted and the field penetrates the sapphire substrate. Chapter 4 describes a more complete two-dimensional model and gives results of programs implementing the model.
Developments in the fields of semiconductors and magnetics are surveyed. Materials, devices, theory, and fabrication technology are discussed. Important events up until the present time are reported, and events are interpreted through historical perspective. A brief analysis of forces which have driven the development of today's electronic technology and some projections of present trends are given. More detailed discussions are presented for four areas of contemporary interest: amorphous semiconductors, bubble domain devices, charge-coupled devices, and electron and ion beam techniques. Beam addressed magnetic memories are reviewed to a lesser extent.
The elementary classical models for idealized diffusion conditions are described, and the principles are then used in developing more realistic models. The practical models require some type of numerical analysis. The numerical techniques are outlined and details concerning their implementation are given. Some results are presented which were obtained with the computer programs implementing the numerical techniques with implicit and explicit methods. Special problems of impurity-rich interlayers forming between an oxide and silicon are considered. A set of computed curves for sheet resistance, junction depth, and oxide thickness for different diffusion schedules is included.