Engineering topics

Gerke, David

Publications and source records attributed to Gerke, David.

6 records

NASA NTRS2009

NASA 2009 Body of Knowledge (BoK) Through-Slicon Via Technology

Through-silicon via (TSV) is the latest in a progression of technologies for stacking silicon devices in three dimensions (3D). Driven by the need for improved performance, methods to use short vertical interconnects to replace the long interconnects found in 2D structures have been developed. The industry is moving past the feasibility (research and development [R and D]) phase for TSV technology into the commercialization phase where economic realities will determine which technologies are adopted. Low-cost fine via hole formation and highly reliable via filling technologies have been demonstrated; process equipment and materials are available. Even though design, thermal, and test issues remain, much progress has been made.

3D packaging↗

NASA NTRS2009

NASA 2009 Body of Knowledge (BoK) carbon nanotube technology

The nature of the bonding of a nanotube is described by applied quantum chemistry, specifically, orbital hybridization. The chemical bonding of nanotubes is composed entirely of sp2 bonds, similar to those of graphite. This bonding structure, which is stronger than the sp3 bonds found in diamonds, provides the molecules with their unique strength. Nanotubes naturally align themselves into "ropes" held together by Van der Waals forces. Under high pressure, nanotubes can merge together, trading some sp² bonds for sp³ bonds, giving the possibility of producing strong, unlimited-length wires through high-pressure nanotube linking. This document looks at the topic of carbon nanotubes as it applies to microelectronics packaging and assembly.

Gerke, David↗

NASA NTRS2009

Evaluation methodology guidance for stack packages

This report provides evaluation methodology guidance based on previous National Aeronautics and Space Administration (NASA) reports and literature surveys for 3D stack packages and assemblies. Two aspects of technology are covered: the package itself (guidance for functional packages) and package assembly manufacturing and reliability. This work was funded by the NASA Electronic Parts and Packaging (NEPP) Program. The objectives of this NEPP project are to: Perform a literature survey of 3D stack technology; perform a literature survey on the evaluation methodology for 3D package and assembly; combine the two aspects to provide evaluation methodology for both aspects with consideration of interactions between package and assembly; generate guidance on the evaluation methodology for 3D stack package integrity prior to and after assembly; provide recommendations on future experimental activities. The qualification and evaluation methodology guidelines will facilitate NASA projects in effectively evaluating the reliability of very dense and newly available high-density 3D stack packages, allowing more processing power in a smaller board footprint and lower system weight.

Gerke, David↗

NASA NTRS2009

Embedded passives emulator FY2003 interim report

The National Aeronautics and Space Administration Electronic Parts and Packaging (NEPP) Program has been evaluating state-of-the-art Embedded Passive Technology for the printed circuit board (PCB) industry for the past several years and has conducted its own testing on embedded passive coupons (resistors and capacitors). This document is a progress report of the work performed through fiscal year 2008 by NASA and the Navy to convert an existing PWB (printed wiring board) design to a design that incorporates embedded passive components. The work is being performed through a memorandum of understanding (MOU) between the NEPP Program (NASA) and the Naval Surface Warfare Center (NSWC) Crane Emerging Critical Interconnect Technology (ECIT) Program. NSWC Crane’s ECIT Program has funding to convert two PCB designs from the military and aerospace industry to a PCB design with embedded passives. ECIT will provide a design team that will take a well characterized design and convert it to an embedded design. They will also provide electrical modeling and layout expertise as well as build the PWB in their facility in Indiana. NEPP, through the Jet Propulsion Laboratory (JPL), will assemble any passives deemed not suitable for embedding and the active components and electrically test the new design to the existing (non-embedded) design

Gerke, David↗

NASA NTRS2008

Embedded ESD Protection Proof of Concept

The purpose of this project is to characterize and correlate Electrostatic Discharge (ESD) sensitivity levels of an Integrated Circuit (IC) package using Transmission Line Pulse (TLP) and Human Body Model (HBM) methods. This characterization will be used as a baseline ESD sensitivity level to demonstrate improvement to the ESD sensitivity of the IC package through the use of EPI-FLO(Trade Mark) Polymer Voltage Suppression (PVS) protection devices developed and manufactured by Electronic Polymers, Inc. (EPI).

Human Body Model (HBM) methods↗

NASA NTRS2005

3-D Packaging: A Technology Review

Traditional electronics are assembled as a planar arrangement of components on a printed circuit board (PCB) or other type of substrate. These planar assemblies may then be plugged into a motherboard or card cage creating a volume of electronics. This architecture is common in many military and space electronic systems as well as large computer and telecommunications systems and industrial electronics. The individual PCB assemblies can be replaced if defective or for system upgrade. Some applications are constrained by the volume or the shape of the system and are not compatible with the motherboard or card cage architecture. Examples include missiles, camcorders, and digital cameras. In these systems, planar rigid-flex substrates are folded to create complex 3-D shapes. The flex circuit serves the role of motherboard, providing interconnection between the rigid boards. An example of a planar rigid - flex assembly prior to folding is shown. In both architectures, the interconnection is effectively 2-D.

Strickland, Mark↗