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Gray, Andrew

Publications and source records attributed to Gray, Andrew.

18 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2018

A Technology Architecture for Accessing the Oceans of Icy Worlds

The icy moon oceans beckon with ingredients that potentially may harbour extant life. Beginning with the Galileo and Cassini missions, measurements have revealed the presence of global oceans under the icy crust of several moons of Jupiter and Saturn. Among those moons, Europa and Enceladus have their ocean in contact with the rocky core, providing an environment similar to the conditions existing on the terrestrial sea-floor where life has developed at hydrothermal vents Accessing these oceans presents considerable difficulty due to a number of issues including the depth and composition of the icy crust, the time needed to travel through the crust, the power needed to propel a probe, communication of scientific and engineering data though the ice and back to Earth, entry and mobility in the ocean and autonomous operations for the life of the mission. A detailed trade space study was conducted to develop a technology architecture defining a system that would access an icy moon’s ocean. To specifically bound the architecture, Jupiter’s moon Europa was chosen as the target body though the work can apply to other bodies. The current understanding of the scientific properties of the ice crust and ocean was used to guide the development. A strawman scientific payload was devised to further develop a baseline set of requirements. Beginning with a launch and trajectory that can bring a system to Europa’s orbit, a complete trade space was developed outlining the engineering systems needed to access the ocean. The architecture was divided into specific phases for i) deorbit, descent and landing, ii) surface operations, iii) ice descent and iv) ocean access. The technical maturity of each of sub-system for the phases was assessed for systems that could be developed to a maturity ready for a preliminary design in less than ten years. Integrated system parameters on power, communication capacity, and mass were developed to further define the overall system. To constrain the design, a total time in the ice, from the ice crust surface to accessing the ocean was limited to three years, and 15Km of ice was baselined with a temperature profile through the ice estimated from the scientific literature.

Sengupta, Anita↗
NASA NTRS2016

Electrospray Thruster Performance with Microfabricated Emitter Arrays and Indium Propellant

The feasibility of a microfabricated indium-fueled electrospray thruster with excellent performance was demonstrated. High efficiency electrospray thrusters with microfabricated components are under development for very compact, distributable propulsion systems that can be employed on both very small and large spacecraft with 10X improvement over SOA in mass, volume and specific impulse The critical components of this technology are the microfabricated emitter arrays and the capillary force driven indium feed system. Grey scale electron-beam lithography patterning and reactive ion dry etching provided the required micron-scale etch precision and uniformity across an array of 400 emitters in 1 cm2. Initial tests of single microfabricated silicon emitters demonstrated better performance than industry standard single emitters and the performance required to achieve 200 micronewtons when scaled up to a thruster with 400 emitters in 1 cm2. Arrays of emitters tested in a preliminary prototype Microfluidic Electrospray Propulsion (MEP) thruster assembly demonstrated stable performance at estimated thrust levels of 5, 50, and 120 µN at extraction voltages less than 4 kV. Current stability was within 0.15 % at 120 µN with only 1.5% of the emitter current collected by the extractor electrode. Post-test inspections revealed that more than 99% of the 400 emitters were electrospraying during the test. Specific impulse was estimated to be >3100 s from measurements of total charge and consumed indium mass at an emitter voltage of 1470 V. The results of this investigation suggest that microfabricated indium electrospray thruster technology is both feasible and capable of excellent performance as a highly compact microthruster.

Marrese-Reading, Colleen M.↗
NASA NTRS2010

Parallel Processing of Broad-Band PPM Signals

A parallel-processing algorithm and a hardware architecture to implement the algorithm have been devised for timeslot synchronization in the reception of pulse-position-modulated (PPM) optical or radio signals. As in the cases of some prior algorithms and architectures for parallel, discrete-time, digital processing of signals other than PPM, an incoming broadband signal is divided into multiple parallel narrower-band signals by means of sub-sampling and filtering. The number of parallel streams is chosen so that the frequency content of the narrower-band signals is low enough to enable processing by relatively-low speed complementary metal oxide semiconductor (CMOS) electronic circuitry. The algorithm and architecture are intended to satisfy requirements for time-varying time-slot synchronization and post-detection filtering, with correction of timing errors independent of estimation of timing errors. They are also intended to afford flexibility for dynamic reconfiguration and upgrading. The architecture is implemented in a reconfigurable CMOS processor in the form of a field-programmable gate array. The algorithm and its hardware implementation incorporate three separate time-varying filter banks for three distinct functions: correction of sub-sample timing errors, post-detection filtering, and post-detection estimation of timing errors. The design of the filter bank for correction of timing errors, the method of estimating timing errors, and the design of a feedback-loop filter are governed by a host of parameters, the most critical one, with regard to processing very broadband signals with CMOS hardware, being the number of parallel streams (equivalently, the rate-reduction parameter).

Gray, Andrew↗
NASA NTRS2010

PPM Receiver Implemented in Software

A computer program has been written as a tool for developing optical pulse-position- modulation (PPM) receivers in which photodetector outputs are fed to analog-to-digital converters (ADCs) and all subsequent signal processing is performed digitally. The program can be used, for example, to simulate an all-digital version of the PPM receiver described in Parallel Processing of Broad-Band PPM Signals (NPO-40711), which appears elsewhere in this issue of NASA Tech Briefs. The program can also be translated into a design for digital PPM receiver hardware. The most notable innovation embodied in the software and the underlying PPM-reception concept is a digital processing subsystem that performs synchronization of PPM time slots, even though the digital processing is, itself, asynchronous in the sense that no attempt is made to synchronize it with the incoming optical signal a priori and there is no feedback to analog signal processing subsystems or ADCs. Functions performed by the software receiver include time-slot synchronization, symbol synchronization, coding preprocessing, and diagnostic functions. The program is written in the MATLAB and Simulink software system. The software receiver is highly parameterized and, hence, programmable: for example, slot- and symbol-synchronization filters have programmable bandwidths.

Gray, Andrew↗
NASA NTRS2009

Parallel-Processing CMOS Circuitry for M-QAM and 8PSK TCM

There has been some additional development of parts reported in "Multi-Modulator for Bandwidth-Efficient Communication" (NPO-40807), NASA Tech Briefs, Vol. 32, No. 6 (June 2009), page 34. The focus was on 1) The generation of M-order quadrature amplitude modulation (M-QAM) and octonary-phase-shift-keying, trellis-coded modulation (8PSK TCM), 2) The use of square-root raised-cosine pulse-shaping filters, 3) A parallel-processing architecture that enables low-speed [complementary metal oxide/semiconductor (CMOS)] circuitry to perform the coding, modulation, and pulse-shaping computations at a high rate; and 4) Implementation of the architecture in a CMOS field-programmable gate array.

Gray, Andrew↗
NASA NTRS2009

Determining Locations by Use of Networks of Passive Beacons

Networks of passive radio beacons spanning moderate-sized terrain areas have been proposed to aid navigation of small robotic aircraft that would be used to explore Saturn s moon Titan. Such networks could also be used on Earth to aid navigation of robotic aircraft, land vehicles, or vessels engaged in exploration or reconnaissance in situations or locations (e.g., underwater locations) in which Global Positioning System (GPS) signals are unreliable or unavailable. Prior to use, it would be necessary to pre-position the beacons at known locations that would be determined by use of one or more precise independent global navigation system(s). Thereafter, while navigating over the area spanned by a given network of passive beacons, an exploratory robot would use the beacons to determine its position precisely relative to the known beacon positions (see figure). If it were necessary for the robot to explore multiple, separated terrain areas spanned by different networks of beacons, the robot could use a long-haul, relatively coarse global navigation system for the lower-precision position determination needed during transit between such areas. The proposed method of precise determination of position of an exploratory robot relative to the positions of passive radio beacons is based partly on the principles of radar and partly on the principles of radio-frequency identification (RFID) tags. The robot would transmit radar-like signals that would be modified and reflected by the passive beacons. The distance to each beacon would be determined from the roundtrip propagation time and/or round-trip phase shift of the signal returning from that beacon. Signals returned from different beacons could be distinguished by means of their RFID characteristics. Alternatively or in addition, the antenna of each beacon could be designed to radiate in a unique pattern that could be identified by the navigation system. Also, alternatively or in addition, sets of identical beacons could be deployed in unique configurations such that the navigation system could identify their unique combinations of radio-frequency reflections as an alternative to leveraging the uniqueness of the RFID tags. The degree of dimensional accuracy would depend not only on the locations of the beacons but also on the number of beacon signals received, the number of samples of each signal, the motion of the robot, and the time intervals between samples. At one extreme, a single sample of the return signal from a single beacon could be used to determine the distance from that beacon and hence to determine that the robot is located somewhere on a sphere, the radius of which equals that distance and the center of which lies at the beacon. In a less extreme example, the three-dimensional position of the robot could be determined with fair precision from a single sample of the signal from each of three beacons. In intermediate cases, position estimates could be refined and/or position ambiguities could be resolved by use of supplementary readings of an altimeter and other instruments aboard the robot.

Okino, Clayton↗
NASA NTRS2009

Multi-Modulator for Bandwidth-Efficient Communication

A modulator circuit board has recently been developed to be used in conjunction with a vector modulator to generate any of a large number of modulations for bandwidth-efficient radio transmission of digital data signals at rates than can exceed 100 Mb/s. The modulations include quadrature phaseshift keying (QPSK), offset quadrature phase-shift keying (OQPSK), Gaussian minimum-shift keying (GMSK), and octonary phase-shift keying (8PSK) with square-root raised-cosine pulse shaping. The figure is a greatly simplified block diagram showing the relationship between the modulator board and the rest of the transmitter. The role of the modulator board is to encode the incoming data stream and to shape the resulting pulses, which are fed as inputs to the vector modulator. The combination of encoding and pulse shaping in a given application is chosen to maximize the bandwidth efficiency. The modulator board includes gallium arsenide serial-to-parallel converters at its input end. A complementary metal oxide/semiconductor (CMOS) field-programmable gate array (FPGA) performs the coding and modulation computations and utilizes parallel processing in doing so. The results of the parallel computation are combined and converted to pulse waveforms by use of gallium arsenide parallel-to-serial converters integrated with digital-to-analog converters. Without changing the hardware, one can configure the modulator to produce any of the designed combinations of coding and modulation by loading the appropriate bit configuration file into the FPGA.

Gray, Andrew↗
NASA NTRS2006

Protocol Sensing Across Multiple Space Missions

In this work, we present sensing performance using an architecture for a reconfigurable protocol chip for spacebased applications. Toward utilizing the IP packet architecture, utilizing data link layer framing structures for multiplexed data on a channel are the targeted application considered for demonstration purposes. Specifically, we examine three common framing standards and present the sensing performance of these standards and their relative de-correlation metrics. Some analysis is performed to investigate the impact of lossy links and on the number of packets required to perform a decision with some probability. Finally, we present results on a demonstration platform that integrated reconfigurable sensing technology into the Ground Station Interface Device (GRID) for End-to-End IP demonstrations in space.

Ground Station Interface Device (GRID)↗
NASA NTRS2006

Reconfigurable Protocol Sensing in an End-to-End Demonstration

In this work, we present sensing performance using an architecture for a reconfigurable protocol chip for spacebased applications. Toward utilizing the IP packet architecture, utilizing data link layer framing structures for multiplexed data on a channel are the targeted application considered for demonstration purposes. Specifically, we examine three common framing standards and present the sensing performance of these standards and their relative de-correlation metrics. Some analysis is performed to investigate the impact of lossy links. Finally, we present results on a demonstration platform that integrated reconfigurable sensing technology into the Ground Station Interface Device (GRID) for End-to-End IP demonstrations in space.

space based applications↗
NASA NTRS2005

Precision ADCS of a spinning spacecraft for the Mars Aeronomy Explorer Mission

This paper discusses a precision attitude and control technique for meeting these requirements utilizing a similar architecture that was adopted for the Laboratory of Atmospheric and Space Physics (LASP) SNOE (Student Nitrous Oxide Explorer) spinning spacecraft; SNOE has been operating with its ADCS architecture in low earth orbit (LEO) for over two years.

Mars Aeronomy Explorer (MAX)↗
NASA NTRS2005

Software-Reconfigurable Processors for Spacecraft

A report presents an overview of an architecture for a software-reconfigurable network data processor for a spacecraft engaged in scientific exploration. When executed on suitable electronic hardware, the software performs the functions of a physical layer (in effect, acts as a software radio in that it performs modulation, demodulation, pulse-shaping, error correction, coding, and decoding), a data-link layer, a network layer, a transport layer, and application-layer processing of scientific data. The software-reconfigurable network processor is undergoing development to enable rapid prototyping and rapid implementation of communication, navigation, and scientific signal-processing functions; to provide a long-lived communication infrastructure; and to provide greatly improved scientific-instrumentation and scientific-data-processing functions by enabling science-driven in-flight reconfiguration of computing resources devoted to these functions. This development is an extension of terrestrial radio and network developments (e.g., in the cellular-telephone industry) implemented in software running on such hardware as field-programmable gate arrays, digital signal processors, traditional digital circuits, and mixed-signal application-specific integrated circuits (ASICs).

Farrington, Allen↗
NASA NTRS2004

Scalable Architecture for Multihop Wireless ad Hoc Networks

A scalable architecture for wireless digital data and voice communications via ad hoc networks has been proposed. Although the details of the architecture and of its implementation in hardware and software have yet to be developed, the broad outlines of the architecture are fairly clear: This architecture departs from current commercial wireless communication architectures, which are characterized by low effective bandwidth per user and are not well suited to low-cost, rapid scaling in large metropolitan areas. This architecture is inspired by a vision more akin to that of more than two dozen noncommercial community wireless networking organizations established by volunteers in North America and several European countries.

Arabshahi, Payman↗
NASA NTRS2004

Finding Minimum-Power Broadcast Trees for Wireless Networks

Some algorithms have been devised for use in a method of constructing tree graphs that represent connections among the nodes of a wireless communication network. These algorithms provide for determining the viability of any given candidate connection tree and for generating an initial set of viable trees that can be used in any of a variety of search algorithms (e.g., a genetic algorithm) to find a tree that enables the network to broadcast from a source node to all other nodes while consuming the minimum amount of total power. The method yields solutions better than those of a prior algorithm known as the broadcast incremental power algorithm, albeit at a slightly greater computational cost.

Arabshahi, Payman↗
NASA NTRS2004

Parallel-Processing Equalizers for Multi-Gbps Communications

Architectures have been proposed for the design of frequency-domain least-mean-square complex equalizers that would be integral parts of parallel- processing digital receivers of multi-gigahertz radio signals and other quadrature-phase-shift-keying (QPSK) or 16-quadrature-amplitude-modulation (16-QAM) of data signals at rates of multiple gigabits per second. Equalizers as used here denotes receiver subsystems that compensate for distortions in the phase and frequency responses of the broad-band radio-frequency channels typically used to convey such signals. The proposed architectures are suitable for realization in very-large-scale integrated (VLSI) circuitry and, in particular, complementary metal oxide semiconductor (CMOS) application- specific integrated circuits (ASICs) operating at frequencies lower than modulation symbol rates. A digital receiver of the type to which the proposed architecture applies (see Figure 1) would include an analog-to-digital converter (A/D) operating at a rate, fs, of 4 samples per symbol period. To obtain the high speed necessary for sampling, the A/D and a 1:16 demultiplexer immediately following it would be constructed as GaAs integrated circuits. The parallel-processing circuitry downstream of the demultiplexer, including a demodulator followed by an equalizer, would operate at a rate of only fs/16 (in other words, at 1/4 of the symbol rate). The output from the equalizer would be four parallel streams of in-phase (I) and quadrature (Q) samples.

Gray, Andrew↗
NASA NTRS2003

Bandwidth Efficient Baseband Multi-Modulator

The High Rate Baseband Multi-Modulator (HRBM) ASIC is being developed to provide High-speed Bandwidth Efficient Modulations to NASA missions. Bandwidth efficiencies from 2.0 bits/symbol/Hz to 2.75 bits/symbl/Hz are selectable from three CCSDS modulations: Gaussian Minimum Shift Keying (GMSK), Filter Offset Quadrature Phase Shift Keying (Filtered- OQSK) and 8-Phase Shift Keying Trellis Coded Modulation (8-PSK TCM). An FPGA version of the HRBM is developed first to verify the individual modulation designs and characterize timing and performance issues involved with digital baseband modulation synthesis. A Finite Input Response (FIR) filter is included to provided baseband pulse shaping to reduce out-of-band spectral emissions. This is filter is programmable and can be tailored to meet system requirements. The ASIC is targeted to provide up to 600 Mbps throughput and will provide serial as well as parallel input. This paper provides an overview of the technology development and current status.

Fong, Wai↗
NASA NTRS2000

Flexible All-Digital Receiver for Bandwidth Efficient Modulations

An all-digital high data rate parallel receiver architecture developed jointly by Goddard Space Flight Center and the Jet Propulsion Laboratory is presented. This receiver utilizes only a small number of high speed components along with a majority of lower speed components operating in a parallel frequency domain structure implementable in CMOS, and can currently process up to 600 Mbps with standard QPSK modulation. Performance results for this receiver for bandwidth efficient QPSK modulation schemes such as square-root raised cosine pulse shaped QPSK and Feher's patented QPSK are presented, demonstrating the flexibility of the receiver architecture.

Gray, Andrew↗
NASA NTRS1998

High Rate Digital Demodulator ASIC

The architecture of High Rate (600 Mega-bits per second) Digital Demodulator (HRDD) ASIC capable of demodulating BPSK and QPSK modulated data is presented in this paper. The advantages of all-digital processing include increased flexibility and reliability with reduced reproduction costs. Conventional serial digital processing would require high processing rates necessitating a hardware implementation in other than CMOS technology such as Gallium Arsenide (GaAs) which has high cost and power requirements. It is more desirable to use CMOS technology with its lower power requirements and higher gate density. However, digital demodulation of high data rates in CMOS requires parallel algorithms to process the sampled data at a rate lower than the data rate. The parallel processing algorithms described here were developed jointly by NASA's Goddard Space Flight Center (GSFC) and the Jet Propulsion Laboratory (JPL). The resulting all-digital receiver has the capability to demodulate BPSK, QPSK, OQPSK, and DQPSK at data rates in excess of 300 Mega-bits per second (Mbps) per channel. This paper will provide an overview of the parallel architecture and features of the HRDR ASIC. In addition, this paper will provide an over-view of the implementation of the hardware architectures used to create flexibility over conventional high rate analog or hybrid receivers. This flexibility includes a wide range of data rates, modulation schemes, and operating environments. In conclusion it will be shown how this high rate digital demodulator can be used with an off-the-shelf A/D and a flexible analog front end, both of which are numerically computer controlled, to produce a very flexible, low cost high rate digital receiver.

Ghuman, Parminder↗