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Grunthaner, Paula

Publications and source records attributed to Grunthaner, Paula.

4 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2004

Chemical Thinning Process for Fabricating UV-Imaging CCDs

The thinning stage of the postfabrication process reported in the immediately preceding article is notable in its own right. Although the thinning process was described in the preceding article as part of an overall process of fabrication of a supported charge-coupled device (CCD), it is more generally applicable to both free-standing and supported devices that have been fabricated in die and wafer formats. Like the thermocompression bonding process described in the preceding article, the thinning process is compatible with CCD-fabrication processes, as well as postfabrication processes that enhance the response of CCDs to ultraviolet (UV) light, including the delta-doping process. CCDs that are thinned by this process and then delta-doped exhibit high quantum efficiencies that are stable with time and with exposure to the environment.

Jones, TOdd↗
NASA NTRS2004

Fabrication of Robust, Flat, Thinned, UV-Imaging CCDs

An improved process that includes a high-temperature bonding subprocess has been developed to enable the fabrication of robust, flat, silicon-based charge-coupled devices (CCDs) for imaging in ultraviolet (UV) light and/or for detecting low-energy charged particles. The CCDs in question are devices on which CCD circuitry has already been formed and have been thinned for backsurface illumination. These CCDs may be delta doped, and aspects of this type of CCD have been described in several prior articles in NASA Tech Briefs. Unlike prior low-temperature bonding subprocesses based on the use of epoxies or waxes, the high-temperature bonding subprocess is compatible with the deltadoping process as well as with other CCD-fabrication processes. The present improved process and its bonding, thinning, and delta-doping subprocesses, are characterized as postfabrication processes because they are undertaken after the fabrication of CCD circuitry on the front side of a full-thickness silicon substrate. In a typical case, it is necessary to reduce the thickness of the CCD to between 10 and 20 m in order to take advantage of back-side illumination and in order to perform delta doping and/or other back-side treatment to enhance the quantum efficiency. In the prior approach to the fabrication of back-side-illuminated CCDs, the thinning subprocess turned each CCD into a free-standing membrane that was fragile and tended to become wrinkled. In the present improved process, prior to thinning and delta doping, a CCD is bonded on its front side to a silicon substrate that has been prefabricated to include cutouts to accommodate subsequent electrical connections to bonding pads on the CCD circuitry. The substrate provides structural support to increase ruggedness and maintain flatness. At the beginning of this process, the back side of a CCD as fabricated on a full-thickness substrate is polished. Silicon nitride is deposited on the back side, opposite the bonding pads on the front side, in order to define a relatively thick frame. The portion of the CCD not covered by the frame is the portion to be thinned by etching.

Grunthaner, Paula↗
NASA NTRS2003

Artifacts for Calibration of Submicron Width Measurements

Artifacts that are fabricated with the help of molecular-beam epitaxy (MBE) are undergoing development for use as dimensional calibration standards with submicron widths. Such standards are needed for calibrating instruments (principally, scanning electron microscopes and scanning probe microscopes) for measuring the widths of features in advanced integrated circuits. Dimensional calibration standards fabricated by an older process that involves lithography and etching of trenches in (110) surfaces of single-crystal silicon are generally reproducible to within dimensional tolerances of about 15 nm. It is anticipated that when the artifacts of the present type are fully developed, their critical dimensions will be reproducible to within 1 nm. These artifacts are expected to find increasing use in the semiconductor-device and integrated- circuit industries as the width tolerances on semiconductor devices shrink to a few nanometers during the next few years. Unlike in the older process, one does not rely on lithography and etching to define the critical dimensions. Instead, one relies on the inherent smoothness and flatness of MBE layers deposited under controlled conditions and defines the critical dimensions as the thicknesses of such layers. An artifact of the present type is fabricated in two stages (see figure): In the first stage, a multilayer epitaxial wafer is grown on a very flat substrate. In the second stage, the wafer is cleaved to expose the layers, then the exposed layers are differentially etched (taking advantage of large differences between the etch rates of the different epitaxial layer materials). The resulting structure includes narrow and well-defined trenches and a shelf with thicknesses determined by the thicknesses of the epitaxial layers from which they were etched. Eventually, it should be possible to add a third fabrication stage in which durable, electronically inert artifacts could be replicated in diamondlike carbon from a master made by MBE and etching as described above.

Grunthaner, Frank↗