Engineering topics
Guo, X.
Publications and source records attributed to Guo, X..
Precision studies of QCD in the low energy domain of the EIC
This White Paper aims at highlighting the important benefits in the science reach of the EIC. High luminosity operation is generally desirable, as it enables producing and harvesting scientific results in a shorter time period. Furthermore, it becomes crucial for programs that would require many months or even years of operation at lower luminosity.
Xuite, Ca3Fe2[(Al,Fe)O3(OH)]3, a new mineral of the garnet group: Implications for the wide occurrence of nanominerals
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High-Performance All-Polymer Solar Cells Enabled by n-Type Polymers with an Ultranarrow Bandgap Down to 1.28 eV
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Plasma physics in the IRCC-AFP collaboration: magnetic reconnection and stellar accretion disks
No abstract provided
Thermodynamic non-ideality and disorder heterogeneity in actinide silicate solid solutions
Non-ideal thermodynamics of solid solutions can greatly impact materials degradation behavior. We have investigated an actinide silicate solid solution system (USiO 4 –ThSiO 4 ), demonstrating that thermodynamic non-ideality follows a distinctive, atomic-scale disordering process, which is usually considered as a random distribution. Neutron total scattering implemented by pair distribution function analysis confirmed a random distribution model for U and Th in first three coordination shells; however, a machine-learning algorithm suggested heterogeneous U and Th clusters at nanoscale (~2 nm). The local disorder and nanosized heterogeneous is an example of the non-ideality of mixing that has an electronic origin. Partial covalency from the U/Th 5f–O 2p hybridization promotes electron transfer during mixing and leads to local polyhedral distortions. The electronic origin accounts for the strong non-ideality in thermodynamic parameters that extends the stability field of the actinide silicates in nature and under typical nuclear waste repository conditions.
Taking evolutionary circuit design from experimentation to implementation: some useful techniques and a silicon demonstration
Current techniques in evolutionary synthesis of analogue and digital circuits designed at transistor level have focused on achieving the desired functional response, without paying sufficient attention to issues needed for a practical implementation of the resulting solution. No silicon fabrication of circuits with topologies designed by evolution has been done before, leaving open questions on the feasibility of the evolutionary circuit design approach, as well as on how high-performance, robust, or portable such designs could be when implemented in hardware. It is argued that moving from evolutionary 'design-for experimentation' to 'design-for-implementation' requires, beyond inclusion in the fitness function of measures indicative of circuit evaluation factors such as power consumption and robustness to temperature variations, the addition of certain evaluation techniques that are not common in conventional design. Several such techniques that were found to be useful in evolving designs for implementation are presented; some are general, and some are particular to the problem domain of transistor-level logic design, used here as a target application. The example used here is a multifunction NAND/NOR logic gate circuit, for which evolution obtained a creative circuit topology more compact than what has been achieved by multiplexing a NAND and a NOR gate. The circuit was fabricated in a 0.5 mum CMOS technology and silicon tests showed good correspondence with the simulations.
On-chip evolutionary synthesis of reconfigurable analog computing circuits
The paper presents a Field Programmable Transistor Array (FPTA), developed as an experimental platform for implementing flexible, reconfigurable analog computing.
Development of consistent equivalent models by mixed-model search
This paper introduces a new approach to the development of equivalent models. Models of various accuracy and simulation speed may be needed in different contexts of design and analysis, or within different simulators.
Evolving circuits in seconds: experiments with a stand-alone board-level evolvable system
The purpose of this paper is twofold: first, to illustrate a stand-alone board-level evolvable system (SABLES) and its performance, and second to illustrate some problems that occur during evolution with real hardware in the loop, or when the intention of the user is not completely reflected in the fitness function.
On two new trends in evolvable hardware: employment of HDL-based structuring, and design of multi-functional circuits
This paper comments on some directions of growth for evolvable hardware, proposes research directions that address the scalability problem and gives examples of results in novel areas approached by EHW.
Systematic chemical variations in large 3AB iron meteorites: Clues to core crystallization
Analysis of numerous individual iron meteorites have shown that fractional crystallization of iron cores result in variations in chemical concentration of the solid core which span several orders of magnitude. The magnitude and direction of the resulting spatial gradients in the core can provide clues to the physical nature of the core crystallization process. We have analyzed suites of samples from three large 3AB irons (Cape York, 58t; Chupaderos, 24t; Morito, 10t) in order to estimate local chemical gradients. Initial results for the concentrations of Ge, Pd, Pt (Massey group), Ir, Au, As, Co, Os, and Rh (Dalhouse group), and P (Arizona group) show significant ranges among the Cape York and Chupaderos samples and marginally significant ranges among the Morito samples. Measurements of Au, Ir, Co, Ni, Cu, Ga, As, W, Re (from UCLA) and Ni and Co (Arizona group) are in progress. We find a spatial Ir gradient in Chupaderos with a magnitude similar to the one reported for Agpalilik (Cape York iron) by Esbensen et al.
An improved distributed arithmetic architecture
Speed requirements have been, and will continue to be, a major consideration in the design of hardware to implement digital signal processing functions like digital filters and transforms like the DFT and DCT. The conventional approach is to increase speed by adding hardware and increasing chip area. The real challenge is to save chip area while still maintaining high speed performance. The approach we propose is based on the distributed arithmetic implementation (DA) of digital filters. The improvement is based on two observations. Firstly, a single memory element can replace several identical memory elements in a fully parallel DA implementation. Secondly, truncation or rounding may be introduced into the computation at strategic points without increasing error unduly. Both of these approaches can be used to attain area savings without impairing speed of operation.