High-speed CMOS camera
A high-speed CMOS camera includes an array of pixel circuits coupled to a photodiode array, an oscillator circuit, and a pattern generator circuit. The pattern generator circuit includes a high speed shift register and a non-overlap generator. The shift register is programmable to produce a pulse train of trigger pulses that defines an interframe and a frame's shutter duration. The non-overlap generator deserializes the incoming pulse train of trigger pulses, and it produces a time-separated reset pulse based on the pulse train of trigger pulses. The shift register is configured to permit the frame durations and the interframe times to be selected arbitrarily over specified ranges in increments of a basic time unit that depends on the oscillator period.