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Hammer, M.

Publications and source records attributed to Hammer, M..

Design and Testing of the Endcap Concentrator ASICs for the CMS High-Granularity Calorimeter Upgrade

A major upgrade of the High-Granularity Calorimeter (HGCAL) in the CMS detector is planned for Long-Shutdown 3 (LS3), currently expected to start in 2026. This upgrade will contain over 6 million channels and the electronics will be required to be low power and to withstand a radiation environment with a High-Energy Hadron flux of 3x10**6 particles per square centimeter per second. The solution to this significant challenge is the two Endcap Concentrator (ECON) ASICs, ECON-T and ECON-D, working in tandem with the HGCROC front-end ASIC. The two ECON ASICs provide critical on-detector data reduction for both the 40 MHz trigger path (ECON-T) and 750 kHz data acquisition path (ECON-D) of the HGCAL. The ASICs are fabricated in 65nm CMOS. They are rad-tolerant to 600 Mrad with low power consumption (<2.5 mW/channel). This presentation will be a comprehensive description of each ECON design, including the infrastructure that they share as well as the elements that make each unique. The presentation will also include functionality and radiation tests for both ASICs, and the first high statistics characterization results from the full production of 75k ECON-D and ECON-T ASICs.

Hoff, James R. [Fermilab] (ORCID:0000000163514592)↗

Functional Verification for Endcap Concentrator ASICs in the High-Granularity Calorimeter Upgrade of CMS

The High-Granularity Calorimeter (HGCAL) of CMS will undergo a major upgrade during Long-Shutdown 3. The Endcap Concentrator (ECON) ASICs represent key elements in the readout chain, processing trigger (ECON-T) and data (ECON-D) streams from the HGCROC to the lpGBT. The ECONs will operate in a radiation environment with a High-Energy Hadron (HEH) flux of $3\cdot10^{6} cm^{-2}s^{-1}$. This contribution describes the Universal Verification Methodology (UVM)-based functional verification of the ECON ASICs focusing on the re-use of existing components to manage the complexity of the verification environment.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Strategies for on-chip digital data compression for X-ray pixel detectors

Here, the continued desire for X-ray pixel detectors with higher frame rates will stress the ability of application-specific integrated circuit (ASIC) designers to provide sufficient off-chip bandwidth to reach continuous frame rates in the 1 MHz regime. To move from the current 10 kHz to the 1 MHz frame rate regime, ASIC designers will continue to pack as many power-hungry high-speed transceivers at the periphery of the ASIC as possible. In this paper, however, we present new strategies to make the most efficient use of the off-chip bandwidth by utilizing data compression schemes for X-ray photon-counting and charge-integrating pixel detectors. In particular, we describe a novel in-pixel compression scheme that converts from analog to digital converter units to encoded photon counts near the photon Poisson noise level and achieves a compression ratio of >1.5x independent of the dataset. In addition, we describe a simple yet efficient zero-suppression compression scheme called "zeromask" (ZM) located at the ASIC's edge before streaming data off the ASIC chip. ZM achieves average compression ratios of >4x, >7x, and >8x for high-energy X-ray diffraction, ptychography, and X-ray photon correlation spectroscopy datasets, respectively. We present the conceptual designs, register-transfer level block diagrams, and the physical ASIC implementation of these compression schemes in 65 nm CMOS. When combined, these two digital compression schemes could increase the effective off-chip bandwidth by a factor of 6-12x.

47 OTHER INSTRUMENTATION↗