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Han, Jin-Woo

Publications and source records attributed to Han, Jin-Woo.

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

Transistor↗

Copper Nanowire Production for Interconnect Applications

A method of fabricating metallic Cu nanowires with lengths up to about 25 micrometers and diameters in a range 20-100 nanometers, or greater if desired. Vertically oriented or laterally oriented copper oxide structures (CuO and/or Cu2O) are grown on a Cu substrate. The copper oxide structures are reduced with 99+ percent H or H2, and in this reduction process the lengths decrease (to no more than about 25 micrometers), the density of surviving nanostructures on a substrate decreases, and the diameters of the surviving nanostructures have a range, of about 20-100 nanometers. The resulting nanowires are substantially pure Cu and can be oriented laterally (for local or global interconnects) or can be oriented vertically (for standard vertical interconnects).

Han, Jin-Woo↗