Engineering topics
He, Yutao
Publications and source records attributed to He, Yutao.
Building a lunar network using a flexible, long-lived Lunar Geophysical Package (LGP)
No abstract provided
The Earth Surface Mineral Dust Source Investigation: An Earth Science Imaging Spectroscopy Mission
The Earth Surface Mineral Dust Source Investigation, EMIT, is planned to operate from the International Space Station starting no earlier than the fall of 2021. EMIT will use visible to short wavelength infrared imaging spectroscopy to determine the mineral composition of the arid land dust source regions of the Earth to advance our knowledge of the radiative forcing effect of these aerosols. Mineral dust emitted into the atmosphere under high wind conditions is an element of the Earth system with many impacts to the Earth’s energy balance, atmosphere, surface, and oceans. The Earth’s mineral dust cycle with source, transport, and deposition phases are studied with advanced Earth System Models. Because the chemical composition, optical and surface properties of soil particles vary strongly with the mineral composition of the source, these models require knowledge of surface soil mineral dust source composition knowledge to accurately understand dust impacts on the Earth system now and in the future. At present, compositional knowledge of the Earth’s mineral dust source regions from existing data sets is uncertain as a result of limited measurements. EMIT will use spectroscopically derived surface mineral composition to update the prescribe boundary conditions for state-of-the-art Earth System Models. The EMIT-initialized models will be used to investigate the impact of direct radiative forcing in the Earth system that depends strongly on the composition of the mineral dust aerosols emitted into the atmosphere. These new measurements and related products will be used to address the EMIT science objectives and made available to the science community for additional investigations. An overview of the EMIT science, development, and mission is presented in this paper.
Compact Low Power Avionics for the Europa Lander Concept and Other Missions to Ocean Worlds
This paper presents the results of NASA’s game-changing technology development entitled “Ultra Low Temperature Electronics” which represents a paradigm shift in spacecraft avionics development. The project has developed compact avionics technologies to address the Command & Data Handling (CDH), Power and Motor Control needs for mission concepts to ocean worlds such as a potential Europa Lander. We addressed this need by developing the key technologies necessary to develop a next generation compact avionics package. The key technologies that we developed significantly reduce the size, weight, power, and cost (SWAP-C) of the avionics package. These technologies will also allow extreme-environment missions to last longer in their environment by reducing the power and energy requirement to keep the avionics warm.
NEXUS Scalable and Distributed Next-Generation Avionics Bus for Space Missions
A paper discusses NEXUS, a common, next-generation avionics interconnect that is transparently compatible with wired, fiber-optic, and RF physical layers; provides a flexible, scalable, packet switched topology; is fault-tolerant with sub-microsecond detection/recovery latency; has scalable bandwidth from 1 Kbps to 10 Gbps; has guaranteed real-time determinism with sub-microsecond latency/jitter; has built-in testability; features low power consumption (< 100 mW per Gbps); is lightweight with about a 5,000-logic-gate footprint; and is implemented in a small Bus Interface Unit (BIU) with reconfigurable back-end providing interface to legacy subsystems. NEXUS enhances a commercial interconnect standard, Serial RapidIO, to meet avionics interconnect requirements without breaking the standard. This unified interconnect technology can be used to meet performance, power, size, and reliability requirements of all ranges of equipment, sensors, and actuators at chip-to-chip, board-to-board, or box-to-box boundary. Early results from in-house modeling activity of Serial RapidIO using VisualSim indicate that the use of a switched, high-performance avionics network will provide a quantum leap in spacecraft onboard science and autonomy capability for science and exploration missions.
Towards a Unified, Scalable, and Highly Capable Next Generation Avionics Interconnect: The NEXUS Approach
No abstract available
Optimized FPGA Implementation of Multi-Rate FIR Filters Through Thread Decomposition
Multi-rate finite impulse response (MRFIR) filters are among the essential signal-processing components in spaceborne instruments where finite impulse response filters are often used to minimize nonlinear group delay and finite precision effects. Cascaded (multistage) designs of MRFIR filters are further used for large rate change ratio in order to lower the required throughput, while simultaneously achieving comparable or better performance than single-stage designs. Traditional representation and implementation of MRFIR employ polyphase decomposition of the original filter structure, whose main purpose is to compute only the needed output at the lowest possible sampling rate. In this innovation, an alternative representation and implementation technique called TD-MRFIR (Thread Decomposition MRFIR) is presented. The basic idea is to decompose MRFIR into output computational threads, in contrast to a structural decomposition of the original filter as done in the polyphase decomposition. A naive implementation of a decimation filter consisting of a full FIR followed by a downsampling stage is very inefficient, as most of the computations performed by the FIR state are discarded through downsampling. In fact, only 1/M of the total computations are useful (M being the decimation factor). Polyphase decomposition provides an alternative view of decimation filters, where the downsampling occurs before the FIR stage, and the outputs are viewed as the sum of M sub-filters with length of N/M taps. Although this approach leads to more efficient filter designs, in general the implementation is not straightforward if the numbers of multipliers need to be minimized. In TD-MRFIR, each thread represents an instance of the finite convolution required to produce a single output of the MRFIR. The filter is thus viewed as a finite collection of concurrent threads. Each of the threads completes when a convolution result (filter output value) is computed, and activated when the first input of the convolution becomes available. Thus, the new threads get spawned at exactly the rate of N/M, where N is the total number of taps, and M is the decimation factor. Existing threads retire at the same rate of N/M. The implementation of an MRFIR is thus transformed into a problem to statically schedule the minimum number of multipliers such that all threads can be completed on time. Solving the static scheduling problem is rather straightforward if one examines the Thread Decomposition Diagram, which is a table-like diagram that has rows representing computation threads and columns representing time. The control logic of the MRFIR can be implemented using simple counters. Instead of decomposing MRFIRs into subfilters as suggested by polyphase decomposition, the thread decomposition diagrams transform the problem into a familiar one of static scheduling, which can be easily solved as the input rate is constant.
High-Throughput, Adaptive FFT Architecture for FPGA-Based Spaceborne Data Processors
Exponential growth in microelectronics technology such as field-programmable gate arrays (FPGAs) has enabled high-performance spaceborne instruments with increasing onboard data processing capabilities. As a commonly used digital signal processing (DSP) building block, fast Fourier transform (FFT) has been of great interest in onboard data processing applications, which needs to strike a reasonable balance between high-performance (throughput, block size, etc.) and low resource usage (power, silicon footprint, etc.). It is also desirable to be designed so that a single design can be reused and adapted into instruments with different requirements. The Multi-Pass Wide Kernel FFT (MPWK-FFT) architecture was developed, in which the high-throughput benefits of the parallel FFT structure and the low resource usage of Singleton s single butterfly method is exploited. The result is a wide-kernel, multipass, adaptive FFT architecture. The 32K-point MPWK-FFT architecture includes 32 radix-2 butterflies, 64 FIFOs to store the real inputs, 64 FIFOs to store the imaginary inputs, complex twiddle factor storage, and FIFO logic to route the outputs to the correct FIFO. The inputs are stored in sequential fashion into the FIFOs, and the outputs of each butterfly are sequentially written first into the even FIFO, then the odd FIFO. Because of the order of the outputs written into the FIFOs, the depth of the even FIFOs, which are 768 each, are 1.5 times larger than the odd FIFOs, which are 512 each. The total memory needed for data storage, assuming that each sample is 36 bits, is 2.95 Mbits. The twiddle factors are stored in internal ROM inside the FPGA for fast access time. The total memory size to store the twiddle factors is 589.9Kbits. This FFT structure combines the benefits of high throughput from the parallel FFT kernels and low resource usage from the multi-pass FFT kernels with desired adaptability. Space instrument missions that need onboard FFT capabilities such as the proposed DESDynl, SWOT (Surface Water Ocean Topography), and Europa sounding radar missions would greatly benefit from this technology with significant reductions in non-recurring cost and risk.
Desirements of Next Generation Spacecraft Interconnects : The JPL NEXUS Perspective
Objectives of NEXUS (NEXt bUS) (1) A research task funded by JPL R&TD program (2) Develop a common highly-capable next generation avionics interconnect with the following features: (a) Transparently compatible with wired, fiber-optic, and RF physical layers (b) A clear and feasible path-to-flight to ensure infusion into future NASA/JPL missions
A High-Throughput, Adaptive FFT Architecture for FPGA-Based Space-Borne Data Processors
Historically, computationally-intensive data processing for space-borne instruments has heavily relied on ground-based computing resources. But with recent advances in functional densities of Field-Programmable Gate-Arrays (FPGAs), there has been an increasing desire to shift more processing on-board; therefore relaxing the downlink data bandwidth requirements. Fast Fourier Transforms (FFTs) are commonly used building blocks for data processing applications, with a growing need to increase the FFT block size. Many existing FFT architectures have mainly emphasized on low power consumption or resource usage; but as the block size of the FFT grows, the throughput is often compromised first. In addition to power and resource constraints, space-borne digital systems are also limited to a small set of space-qualified memory elements, which typically lag behind the commercially available counterparts in capacity and bandwidth. The bandwidth limitation of the external memory creates a bottleneck for a large, high-throughput FFT design with large block size. In this paper, we present the Multi-Pass Wide Kernel FFT (MPWK-FFT) architecture for a moderately large block size (32K) with considerations to power consumption and resource usage, as well as throughput. We will also show that the architecture can be easily adapted for different FFT block sizes with different throughput and power requirements. The result is completely contained within an FPGA without relying on external memories. Implementation results are summarized.
Optimized FPGA Implementation of Multi-Rate FIR Filters Through Thread Decomposition
No abstract available
Optimized FPGA Implementation of Multi-Rate FIR Filters Through Thread Decomposition
Multirate (decimation/interpolation) filters are among the essential signal processing components in spaceborne instruments where Finite Impulse Response (FIR) filters are often used to minimize nonlinear group delay and finite-precision effects. Cascaded (multi-stage) designs of Multi-Rate FIR (MRFIR) filters are further used for large rate change ratio, in order to lower the required throughput while simultaneously achieving comparable or better performance than single-stage designs. Traditional representation and implementation of MRFIR employ polyphase decomposition of the original filter structure, whose main purpose is to compute only the needed output at the lowest possible sampling rate. In this paper, an alternative representation and implementation technique, called TD-MRFIR (Thread Decomposition MRFIR), is presented. The basic idea is to decompose MRFIR into output computational threads, in contrast to a structural decomposition of the original filter as done in the polyphase decomposition. Each thread represents an instance of the finite convolution required to produce a single output of the MRFIR. The filter is thus viewed as a finite collection of concurrent threads. The technical details of TD-MRFIR will be explained, first showing its applicability to the implementation of downsampling, upsampling, and resampling FIR filters, and then describing a general strategy to optimally allocate the number of filter taps. A particular FPGA design of multi-stage TD-MRFIR for the L-band radar of NASA's SMAP (Soil Moisture Active Passive) instrument is demonstrated; and its implementation results in several targeted FPGA devices are summarized in terms of the functional (bit width, fixed-point error) and performance (time closure, resource usage, and power estimation) parameters.
ISAAC - A Case of Highly-Reusable, Highly-Capable Computing and Control Platform for Radar Applications
ISAAC is a highly capable, highly reusable, modular, and integrated FPGA-based common instrument control and computing platform for a wide range of instrument needs as defined in the Earth Science National Research Council (NRC) Decadal Survey Report. This paper presents its motivation, technical approach, and the infrastructure elements. It also describes the first prototype, ISAAC I, and its application in the design of SMAP L-band radar digital filter.
SMAP's Radar OBP Algorithm Development
An approach for algorithm specifications and development is described for SMAP's radar onboard processor with multi-stage demodulation and decimation bandpass digital filter. Point target simulation is used to verify and validate the filter design with the usual radar performance parameters. Preliminary FPGA implementation is also discussed.
Micro-Inspector Avionics Module (MAM): A Self-Contained Low Power, Reconfigurable Avionics Platform for Small Spacecrafts and Instruments
This paper describes development of a radiation tolerant, low power, reconfigurable avionics module aimed at meeting the avionics needs of the JPL Micro-Inspector spacecraft. This module represents a complete avionics system, consisting of two PowerPC 405 CPUs embedded within a reconfigurable FPGA fabric of over 8 Million logic gates, 64MB of EDAC protected Flash storage and 128MB of EDAC protected DDR SDRAM or SDRAM memories, along with FPGA SEU mitigation logic, and all necessary power conversion. Processor SEU mitigation is achieved by running the two processors in a lock-step and compare configuration. All of these building blocks are integrated into a double sided circuit board that takes as little as 6 square inches of board space. This module can be embedded into a user system as part of a bigger circuit assembly or as a self contained module. This module is being developed as part of a JPL led Micro-Inspector Program, funded by NASA ESMD aimed at producing a 10Kg micro spacecraft.