Improving the infusion of new technologies into space missions
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technology infusion requirements risk cost/benefit↗
Engineering topics
Hicks, K. A.
Publications and source records attributed to Hicks, K. A..
Software support for improving technology infusion
This paper focuses on describing the custom software tool, DDP, that was developed to support the TIMA process, and on showing how the needs of the TIMA process have influenced the development of the structure and capabilities of the DDP software.
requirements risk decision-making tradeoffs↗
Risk-based technology roadmapping
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risk technology infusion decision-making risk miti↗
Risk-based approach for estimating the cost of new technology
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cost technology↗
DDP - a tool for life-cycle risk management
At JPL we have developed, and implemented, a process for achieving life-cycle risk management. This process has been embodied in a software tool and is called Defect Detection and Prevention (DDP). The DDP process can be succinctly stated as: determine where we want to be, what could get in the way and how we will get there.
DDP risk management↗
Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics
Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.
Buehler, M. G.↗
A CMOS matrix for extracting MOSFET parameters before and after irradiation
An addressable matrix of 16 n- and 16 p-MOSFETs was designed to extract the dc MOSFET parameters for all dc gate bias conditions before and after irradiation. The matrix contains four sets of MOSFETs, each with four different geometries that can be biased independently. Thus the worst-case bias scenarios can be determined. The MOSFET matrix was fabricated at a silicon foundry using a radiation-soft CMOS p-well LOCOS process. Co-60 irradiation results for the n-MOSFETs showed a threshold-voltage shift of -3 mV/krad(Si), whereas the p-MOSFETs showed a shift of 21 mV/krad(Si). The worst-case threshold-voltage shift occurred for the n-MOSFETs, with a gate bias of 5 V during the anneal. For the p-MOSFETs, biasing did not affect the shift in the threshold voltage. A parasitic MOSFET dominated the leakage of the n-MOSFET biased with 5 V on the gate during irradiation. Co-60 test results for other parameters are also presented.
Blaes, B. R.↗
CMOS Process Monitor
A CMOS Process Monitor, consisting of eight basic test structures, has been prepared to acquire key CMOS parameters to assist in VLSI wafer acceptance. The test structures can be probed using a 2 by N probe pad array and can be arranged to fit into either the interior or the scribe lane of an integrated circuit chip. In order to facilitate the general use of the monitor, a document is being prepared that describes its design, layout, measurement, and analysis. This paper describes the structures included in the monitor, the methodology used to create the monitor, and test results from the monitor.
Buehler, M. G.↗