Design and first test results of the CMS HGCAL on-detector ECON-T ASIC with a reconfigurable encoder algorithm for data compression [Poster]
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Mantilla Suárez, Mantilla Ana↗
Engineering topics
Hoff, Jim
Publications and source records attributed to Hoff, Jim.
The COLDATA Concentrator ASIC for the Deep Underground Neutrino Experiment [Poster]
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Hoff, Jim↗
An FPGA-based Pattern Recognition Associative Memory
Pattern recognition associative memory (PRAM) devices are parallel processing engines which are used to tackle the complex combinatorics of track nding algorithms, particularly for silicon based tracking triggers. PRAM development has been mostly limited to the realm of ASICs, which often leads to lengthy and expensive design cycles. FPGAs allow for quick iterations, making them an ideal hardware platform for designing and evaluating new PRAM features before committing to silicon. In this paper we present our FPGA-based PRAM designs and discuss how logic blocks which were originally developed for ASICs have been redesigned to take advantage of modern FPGA architectures.
43 PARTICLE ACCELERATORS↗