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Engineering topics

Jiang, Chun Sheng

Publications and source records attributed to Jiang, Chun Sheng.

High-Performance Passivating Contacts for Si PV Based on Engineered, Doped Nanopinholes through Dielectric Layers

We present a novel, industrially relevant method to fabricate high-performance poly-Si passivating contacts for Si PV. Passivating contacts based on SiOx/poly-Si layer stacks have been implemented in record-efficiency homojunction Si solar cells. In this technology, the carrier transport through a surface-passivating SiOx is enabled either by quantum-tunneling or nanopinholes. The doped poly-Si layer provides charge-carrier selectivity. Previously, the ISFH research group demonstrated a record 26.1% efficient Si homojunction cell, where transport pinholes in ~2 nm SiOx were produced by thermal breakdown at > 1000 degrees C, which is hard to control and is surface morphology-dependent. At room temperature, our new process uses electroless plating of Ag nanoparticles, followed by metal-assisted chemical etching. Nanogalvanic corrosion yields < 20 nm-wide nanopinholes in an insulating > 2 nm SiOx layer. The nanopinholes are filled by a heavily doped a-Si:H overlayer. We drive in the dopants into the Si wafer with subsequent high-temperature annealing. Preferential incorporation of dopants at pinhole locations results in nanoscale p+/n or n+/n junctions near the wafer interface. Each heavily-doped nanoscale pinhole junction collects and transports photogenerated carriers to the cell metal contacts. The density of the engineered nanopinholes can be tuned over a wide range which is critical for optimization of device performance. The same nanogalvanic corrosion principles can be applied to produce doped transport pinholes in well-passivating thick dielectric SiOx/SiNy stacks. Importantly, our process does not rely on thermal breakdown of the dielectric layers and can be applied to textured wafers resulting in Si solar cells with > 20% conversion efficiency.

dielectric layer↗

Epitaxial Dirac Semimetal Vertical Heterostructures for Advanced Device Architectures

Exploiting the extraordinary transport and optical properties of 3D topological semimetals for device applications requires epitaxial integration with semiconductors to carefully control carrier transport, yet no studies have established heteroepitaxy on top of any topological semimetals to date. Here, a novel approach toward fabricating heterostructures is demonstrated by epitaxially incorporating the Dirac semimetal Cd 3 As 2 between Zn x Cd 1-x Te and CdTe layers via molecular beam epitaxy on GaAs (001) substrates. The approach utilizes the higher energy (001) surface of Cd 3 As 2 to stabilize 2D epitaxy of zinc blende semiconductors. To demonstrate the impact heterostructure formation offers to device performance, an all-epitaxial, barrier-type vertical photodetector is fabricated that accesses a different carrier separation mechanism than previously reported non-epitaxial junctions and consequently exhibits significantly reduced dark currents. Finally, the results highlight the important role that epitaxial integration can play in accessing advanced architectures for topological semimetal-based devices.

36 MATERIALS SCIENCE↗

Multiscale Materials Characterization

The National Renewable Energy Laboratory (NREL) is advancing the state of the art in multiscale characterization to solve critical issues in materials science. We enthusiastically welcome industry, manufacturing, and government enterprises to partner with us on design integration that ranges from materials selection to manufacturing to reliability.

characterization↗