Investigation on gate oxide reliability under gate bias screening for commercial SiC planar and trench MOSFETs
This paper evaluates the impact of the fast high gate-voltage screening technique on gate oxide reliability of commercial 1.2 kV 4H-SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The measurements are conducted on packaged devices with the intent that the results will be applicable to wafer-level screening. The threshold voltage (V th ) of SiC MOSFETs is measured before and after various screening treatments and recovery process. In addition, constant-voltage time-dependent dielectric breakdown (TDDB) measurements are performed on SiC MOSFETs to obtain the intrinsic lifetime of gate oxide. The objective of this study is to determine the optimal screening conditions and improve screening efficiency without degradation of gate oxide reliability, such as V th shift and reduced oxide intrinsic lifetime. Due to the differences in the gate oxidation process and structural design of SiC planar and trench MOSFETs, the two types of devices exhibit different oxide reliability in the screening process. The recommended screening conditions obtained in this paper reveal that SiC trench MOSFETs can accept higher screening voltages compared to SiC planar MOSFETs. Hence, it can be concluded that more efficient screening techniques can be adopted for SiC MOSFETs with thicker gate oxide to meet the requirements of industrial applications.