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Jin-Woo Han

Publications and source records attributed to Jin-Woo Han.

5 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2021

A Nanoscale Vacuum Field Emission Gated Diode with an Umbrella Cathode

A nanoscale field emission vacuum channel gated diode structure is proposed and a tungsten cathode with an umbrella-like geometry and sharp vertical edge is fabricated. The edge of the suspended cathode becomes the field emission surface. Unlike in the traditional transistor with the gate typically located between the source and the drain, the bottom silicon plate becomes the gate here and the anode terminal is located between the umbrella cathode and the gate. The fabricated devices show excellent diode characteristics and the gated diode structure is attractive for extremely low gate leakage.

Vacuum field emission diode↗
NASA NTRS2018

Electrical Response Using Nanotubes on a Fibrous Substrate

A device produces an electrical signal in response to a stimulus. The device is formed of a flexible substrate including a layer of fibers, for example, paper, and a solution of dispersed carbon nanotubes coated onto and within the fibers, the solution evaporated to leave carbon nanotubes intertwined within the layer of fibers. The carbon nanotubes are functionalized to be optimized for producing an electrical signal for a particular stimulus, where the stimulus includes exposure of the device to a particular gas or vapor. A number of such devices, some or all of which can be different, are housed together, for producing a complex electronic signal, or for sensing any of a wide variety of stimulus.

Jin-Woo Han↗
NASA NTRS2018

One Time Programmable Antifuse Memory Based on Bulk Junctionless Transistor

One time programmable (OTP) antifuse base memory is demonstrated based on a bulk junctionless gate-all-around (GAA) nanowire transistor technology. The presented memory consists of a single transistor (1T) footprint without any process modification. The source/drain (S/D) and gate respectively become bit line and word line where the antifuse is formed by oxide breakdown across the gate and the channel. The channel is connected directly to the bit line due to junctionless S/D and inherently isolated from the neighboring cell by the GAA channel. Therefore, an array of 1T antifuse OTP can be a candidate for the sub-5-nanometer technology node.

Antifuse↗