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Kailath, T.

Publications and source records attributed to Kailath, T..

4 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1989

A family of new efficient arrays for matrix multiplication

The authors present a regular iterative algorithm for matrix multiplication and show that several well-known matrix multiplication arrays are directly obtained from it, differing only in the choice of iteration vector. They then present a regular iterative algorithm for matrix multiplication using the method of Winograd (1968) and show in detail how to derive one array from this algorithmic description. Other arrays in the same family can similarly be obtained for different choices of the iteration space. The new arrays compute the product of two matrices faster than available conventional arrays and use a smaller number of processor cells.

Jagadish, H. V.↗
NASA NTRS1986

A study of pipelining in computing arrays

Scheduling considerations in computing arrays are examined. A simple sufficient condition is developed for determining whether a computing array can be pipelined. If the array cannot be pipelined in the form given, the condition also indicates the direction in which to proceed to make it pipelineable. The overall framework and methodology take a good part of the load off the logical architect of the array, and make the translation from the logical to the physical architecture a mechanical process.

Jagadish, H. V.↗
NASA NTRS1985

Mesh-connected processor arrays for the transitive closure problem

The main purpose in this paper is to lay a theoretical foundation for the design of mesh-connected processor arrays for the transitive closure problem. Using a simple path-algebraic formulation of the problem and observing its similarity to certain well-known smoothing problems that occur in digital signal processing, it is shown how to draw upon existing techniques from the signal processing literature to derive regular iterative algorithms for determining the transitive closure of the graph. The regular iterative algorithms that are derived using these considerations, are then analyzed and synthesized on mesh-connected processor arrays. Among the vast number of mesh-connected processor arrays that can be designed using this unified approach, the systolic arrays reported in the literature for this problem are shown to be special cases.

Rao, S. K.↗