Krasowski, Michael J.

DOE OSTI2021

Two and three-dimensional near infrared subcutaneous structure imager using realtime nonlinear video processing

A method includes placing an imaging device in contact with a sample, irradiating the sample via an illuminator such that radiation scatters off of the structure, and providing the scattered radiation to a detector to generate a digital video signal. A processor then performs various operations including subtracting a sum of a black state value and a user-defined black level clamping value from the digital video signal to create subtracted image data, substituting negative values in the subtracted image data with a reference value to create modified image data, and amplifying the modified image data by a user-defined gain to create contrast enhanced image data.

Krasowski, Michael J.↗

NASA NTRS2019

NASA Innovative Advanced Concepts (NIAC) Phase 1 Final Report: Venus Landsailer Zephyr

Imagine sailing across the hot plains of Venus! A design for a craft to do just this was completed by the COncurrent Multidisciplinary Preliminary Assessment of Space Systems (COMPASS) Team for the NASA Innovative Advanced Concepts (NIAC) project. The robotic craft could explore over 30 km of surface of Venus, driven by the power of the wind.

Landis, Geoffrey A.↗

NASA NTRS2018

Current Source Logic Gate

A current source logic gate with depletion mode field effect transistor ("FET") transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.

Krasowski, Michael J.↗

NASA NTRS2018

Apparatus and Method for Communication over Power Lines

An apparatus and method are provided for communicating over power lines. The apparatus includes a coupling modem that is situated between a power line and a device. The coupling modem is configured to demodulate a signal received from the power line into a sine signal and a cosine signal. The coupling modem is also configured to modulate a communicated bit stream received from the device into a transmitted signal in order to impose the transmitted signal onto the power line.

Krasowski, Michael J.↗

NASA NTRS2018

Demonstration of 4H-SiC JFET Digital ICs Across 1000 °C Temperature Range Without Change to Input Voltages

Operational testing of prototype 4H-SiC JFET ICs across an unrivaled ambient temperature span in excess of 1000 °C, from -190 °C to +812 °C, has been demonstrated without any change/adjustment of input signal levels or power supply voltages. This unique ability is expected to simplify infusion of this IC technology into a broader range of beneficial applications.

Neudeck, Philip G.↗

NASA NTRS2018

Yearlong 500 C Operational Demonstration of Up-Scaled 4H-SiC JFET Integrated Circuits

This work describes recent progress in the design, processing, and testing of significantly up-scaled 500 C durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for over one year at 500 C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500 C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.

Silicon carbides↗

NASA NTRS2018

Yearlong 500 °C Operational Demonstration of Up-Scaled 4H-SiC JFET Integrated Circuits

This work describes recent progress in the design, processing, upscaling, and testing of 500°C durable two-level interconnect 4H-SiC JFET IC technology undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for 1 year (8760 hours) at 500°C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016.

Neudeck, Philip G.↗

NASA NTRS2017

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10 change in output characteristics for the remainder of 500C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Silicon Carbid↗

NASA NTRS2017

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Spry, David J.↗

NASA NTRS2017

Current Source Logic Gate

A current source logic gate with depletion mode field effect transistor ("FET") transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.

Krasowski, Michael J.↗

NASA NTRS2017

Apparatus and Method for Communication over Power Lines

An apparatus and method are provided for communicating over power lines. The apparatus includes a coupling modem that is situated between a power line and a device. The coupling modem is configured to demodulate a signal received from the power line into a sine signal and a cosine signal. The coupling modem is also configured to modulate a communicated bit stream received from the device into a transmitted signal in order to impose the transmitted signal onto the power line.

Krasowski, Michael J.↗

NASA NTRS2016

Method and Apparatus for In-Situ Health Monitoring of Solar Cells in Space

Embodiments of the present invention describe an apparatus including an oscillator, a ramp generator, and an inverter. The oscillator is configured to generate a waveform comprising a low time and a high time. The inverter is configured to receive the waveform generated by the oscillator, and invert the waveform. The ramp generator is configured to increase a gate control voltage of a transistor connected to a solar cell, and rapidly decrease the gate control voltage of the transistor. During the low time, a measurement of a current and a voltage of the solar cell is performed. During the high time, a measurement of a current of a shorted cell and a voltage reference is performed.

Krasowski, Michael J.↗

NASA NTRS2016

Further Analyses of the NASA Glenn Research Center Solar Cell and Photovoltaic Materials Experiment Onboard the International Space Station

Accurate air mass zero (AM0) measurement is essential for the evaluation of new photovoltaic (PV) technology for space solar cells. The NASA Glenn Research Center (GRC) has flown an experiment designed to measure the electrical performance of several solar cells onboard NASA Goddard Space Flight Center's (GSFC) Robotic Refueling Mission's (RRM) Task Board 4 (TB4) on the exterior of the International Space Station (ISS). Four industry and government partners provided advanced PV devices for measurement and orbital environment testing. The experiment was positioned on the exterior of the station for approximately eight months, and was completely self-contained, providing its own power and internal data storage. Several new cell technologies including four-junction (4J) Inverted Metamorphic Multi-Junction (IMM) cells were evaluated and the results will be compared to ground-based measurement methods.

multi-junction↗

NASA NTRS2016

NASA Glenn Research Center Solar Cell Experiment Onboard the International Space Station

Accurate air mass zero (AM0) measurement is essential for the evaluation of new photovoltaic (PV) technology for space solar cells. The NASA Glenn Research Center (GRC) has flown an experiment designed to measure the electrical performance of several solar cells onboard NASA Goddard Space Flight Center's (GSFC) Robotic Refueling Missions (RRM) Task Board 4 (TB4) on the exterior of the International Space Station (ISS). Four industry and government partners provided advanced PV devices for measurement and orbital environment testing. The experiment was positioned on the exterior of the station for approximately eight months, and was completely self-contained, providing its own power and internal data storage. Several new cell technologies including four-junction (4J) Inverted Metamorphic Multi-junction (IMM) cells were evaluated and the results will be compared to ground-based measurement methods.

Solar Cell Calibration Facility↗

NASA NTRS2016

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over approximately 1-micrometer scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

Microelectronics↗

NASA NTRS2015

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

Silicon Carbide↗

NASA NTRS2015

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

JFET↗

NASA NTRS2015

Apparatus and Method for Communication over Power Lines

An apparatus and method are provided for communicating over power lines. The apparatus includes a coupling modem that is situated between a power line and a device. The coupling modem is configured to demodulate a signal received from the power line into a sine signal and a cosine signal. The coupling modem is also configured to modulate a communicated bit stream received from the device into a transmitted signal in order to impose the transmitted signal onto the power line.

Krasowski, Michael J.↗