Engineering topics

Lahmeyer, C. R.

Publications and source records attributed to Lahmeyer, C. R..

5 records

NASA NTRS1988

Long decoding runs for Galileo's convolutional codes

Decoding results are described for long decoding runs of Galileo's convolutional codes. A 1 k-bit/sec hardware Viterbi decoder is used for the (15, 1/4) convolutional code, and a software Viterbi decoder is used for the (7, 1/2) convolutional code. The output data of these long runs are stored in data files using a data compression format which can reduce file size by a factor of 100 to 1 typically. These data files can be used to replicate the long, time-consuming runs exactly and are useful to anyone who wants to analyze the burst statistics of the Viterbi decoders. The 1 k-bit/sec hardware Viterbi decoder was developed in order to demonstrate the correctness of certain algorithmic concepts for decoding Galileo's experimental (15, 1/4) code, and for the long-constraint-length codes in general. The hardware decoder can be used both to search for good codes and to measure accurately the performance of known codes.

Lahmeyer, C. R.↗

NASA NTRS1987

Survey of current correlators and applications

With this summary an attempt is made to contact as many users as possible so as to provide summary data on correlation systems, both in use and as planned. Data on currently available very large scale integration (VLSI) chips and complete systems are included. Also, several planned correlator systems are described and summarized in tabular form. Finally, a description is given of the work being done in the Communications Systems Research Section on VLSI correlator chips and complete correlator systems.

Lahmeyer, C. R.↗

NASA NTRS1986

A systolic architecture for the correlation and accumulation of digital sequences

A fully systolic architecture for the implementation of digital sequence correlator/accumulators is described. These devices consist of a two-dimensional array of processing elements that are conceived for efficient fabrication in Very Large Scale Integrated (VLSI) circuits. A custom VLSI chip that was implemented using these concepts is described. The chip, which contains a four-lag three-level sequence correlator and four bits of accumulation with overflow detection, was designed using the Integrated UNIX-Based Computer Aided Design (CAD) System. Applications of such devices include the synchronization of coded telemetry data, alignment of both real time and non-real time Very Large Baseline Interferometry (VLBI) signals, and the implementation of digital filters and processes of many types.

Deutsch, L. J.↗

NASA NTRS1985

Fast Control Sequencer

Unit faster than conventional circuits and contains fewer integrated circuits. Fast logic controller accommodates three delays before second half cycle of clock signal strobes status latch: Outputs of pipeline register must settle; selected input status line signal must propagate through status multiplexer and arrive at status latch; and it takes 3 nanoseconds for status latch set up before strobed. During second half cycle, output-enable line produces next instruction and applies it to pipeline register.

Lahmeyer, C. R.↗

NASA NTRS1985

Real-Time Reed-Solomon Decoder

RS decoder uses dedicated hardware and data pipelining for high-speed operation. Parallel processing techniques provide equivalent of over one billion operations per second at one step in decoding. Decoder finds commercial application in data encoding/decoding, telemetry, and radio communications.

Lahmeyer, C. R.↗