Engineering topics
Publications and source records attributed to Lee, F. C. Y..
The J3 SCR model is a continuous topology computer model for the SCR. Its circuit analog and parameter estimation procedure are uniformly applicable to popular computer-aided design and analysis programs such as SPICE2 and SCEPTRE. The circuit analog is based on the intrinsic three pn junction structure of the SCR. The parameter estimation procedure requires only manufacturer's specification sheet quantities as a data base.
The present investigation is concerned with an important class of power conditioning networks, taking into account self-oscillating dc-to-square-wave transistor inverters. The considered circuits are widely used both as the principal power converting and processing means in many systems and as low-power analog-to-discrete-time converters for controlling the switching of the output-stage semiconductors in a variety of power conditioning systems. Aspects of piecewise-linear modeling are discussed, taking into consideration component models, and an equivalent-circuit model. Questions of singular point analysis and state plane representation are also investigated, giving attention to limit cycles, starting circuits, the region of attraction, a hard oscillator, and a soft oscillator.
State-space techniques are employed to derive accurate models for the three basic switching converter power stages: buck, boost, and buck/boost operating with and without zero-inductor-current dwell time. A generalized procedure is developed which treats the continuous-inductor-current mode without dwell time as a special case of the discontinuous-current mode when the dwell time vanishes. Abrupt changes of system behavior, including a reduction of the system order when the dwell time appears, are shown both analytically and experimentally. Merits resulting from the present modeling technique in comparison with existing modeling techniques are illustrated.
The paper deals with a NASA-sponsored, computer-based program Modeling and Analysis of Power Processing Systems (MAPPS). Three major MAPPS subprograms, Design Optimization, Control Design, and Performance Analysis are considered. The program makes it possible to reduce the design, analysis, and development time, and thus the cost, in achieving the required performance for power processing equipment and systems.
Utilizing the demonstrated capability of nonlinear programming algorithms, a practical design optimization approach for power converters is established to conceive a design to meet all power-circuit performance requirements and concurrently optimize a defined quantity such as weight or losses. In addition, to facilitate a cost-effective design, the computer-aided approach provides a means to readily assess (1) the weight-efficiency tradeoff, (2) impacts of converter requirements and component characteristics on a given design, and (3) optimum power system configurations.
A methodology for optimizing power-processor designs is described which achieves optimization with respect to some power-processor characteristic deemed particularly desirable by the designer, such as weight or efficiency. Optimization theory based on Lagrange multipliers is reviewed together with nonlinear programming techniques employing penalty functions. The methodology, the task of which is to minimize an objective function subject to design constraints, is demonstrated with the aid of four examples: optimum-weight core selection for an inductor with a predetermined winding size, optimum-weight inductor design with a given loss constraint, optimum-loss inductor design with a given weight constraint, and a comparison of optimum-weight single- and two-stage input-filter designs with identical loss and other requirement constraints. Closed-form solutions for the first three examples are obtained by applying the Lagrange-multiplier method, but solutions for the last example are found numerically through the use of the sequential unconstrained minimization technique.
Four widely used self-oscillating dc-to-square-wave parallel inverters which employ an inductor-capacitor tuned network to determine the oscillation frequency are reduced to a common equivalent RLC network, The techniques of singular-point analysis and state-plane interpretations are employed to describe the steady-state and transient behavior of these circuits and to elucidate the three possible modes of operation: quasi-harmonic, relaxation, and discontinuous. Design guidelines are provided through a study of the influence of circuit parameter variations on the characteristics of oscillation and on frequency stability. Several examples are provided to illustrate the usefulness of this analysis when studying such problems as transistor emitter-to-base junction breakdown during oscillations and the design of starting circuits to insure self-excited oscillations in these inverters.
It recently has been shown in the literature that many dc-to-square-wave parallel inverters which are widely used in power-conditioning applications can be grouped into one of two families. Each family is characterized by an equivalent RLC network. Based on this approach, a classification procedure is presented for self-oscillating parallel inverters which makes evident natural relationships which exist between various inverter configurations. By utilizing concepts from the basic theory of negative resistance oscillators and the principle of duality as applied to nonlinear networks, a chain of relationships is established which enables a methodical transfer of knowledge gained about one family of inverters to any of the other families in the classification array.
Unwanted and sometimes damaging high-amplitude voltage spikes occur during each half cycle in many transistor saturable-core inverters at the moment when the core saturates and the transistors switch. The analysis shows that spikes are an intrinsic characteristic of certain types of inverters even with negligible leakage inductance and purely resistive load. The small but unavoidable after-saturation inductance of the saturable-core transformer plays an essential role in creating these undesired thigh-voltage spikes. State-plane analysis provides insight into the complex interaction between core and transistors, and shows the circuit parameters upon which the magnitude of these spikes depends.
A family of four dc-to-square-wave LC tuned inverters are analyzed using singular point. Limit cycles and waveshape characteristics are given for three modes of oscillation: quasi-harmonic, relaxation, and discontinuous. An inverter in which the avalanche breakdown of the transistor emitter-to-base junction occurs is discussed and the starting characteristics of this family of inverters are presented. The LC tuned inverters are shown to belong to a family of inverters with a common equivalent circuit consisting of only three 'series' elements: a five-segment piecewise-linear current-controlled resistor, linear inductor, and linear capacitor.
A procedure is developed for classifying dc-to-square-wave two-transistor parallel inverters used in power conditioning applications. The inverters are reduced to equivalent RLC networks and are then grouped with other inverters with the same basic equivalent circuit. Distinction between inverter classes is based on the topology characteristics of the equivalent circuits. Information about one class can then be extended to another class using the basic oscillation theory and the concept of duality. Oscillograms from test circuits confirm the validity of the procedure adopted.
A family of five static dc-to-square-wave inverters, each employing a square-loop magnetic core in conjunction with two switching transistors, is analyzed using piecewise-linear models for the nonlinear characteristics of the transistors, diodes, and saturable-core devices. Four of the inverters are analyzed in detail for the first time. These analyses show that, by proper choice of a frame of reference, each of the five quite differently appearing inverter circuits can be described by a common equivalent circuit. This equivalent circuit consists of a five-segment nonlinear resistor, a nonlinear saturable reactor, and a linear capacitor. Thus, by proper interpretation and identification of the parameters in the different circuits, the results of a detailed solution for one of the inverter circuits provide similar information and insight into the local and global behavior of each inverter in the family.
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A dc-to-dc regulated-converter circuit employing duty-cycle control with variable on and variable off time has been presented. A unique feature of this converter is the method by which the bistable-comparator output controls the duty cycle of the power switching transistor through the action of the encoder. The utilization of minor-loop flux excursions of a saturable-core transformer in the encoder makes it feasible to extend the converter switching frequency considerably higher than would normally be possible. With this converter circuit, high and very-high frequency converter operations were explored.