Lee, Wing | Search NASA

NASA NTRS2018

Performance of Variable Coded Modulations over a Nonlinear Channel for VCM Protocol Red Book

This presentation provides a summary of the results obtained from a study which evaluates the performance of variable coded modulations specified in the "Variable Coded Modulation Protocol" CCSDS Red Book, over a nonlinear channel that is currently on the CCSDS Blue Book track. The objectives are to perform simulation that identifies the operating signal-to-noise-power ratio required to achieve a codeword error rate of 1e-4 over the specified nonlinear channel for various modulations (i.e. BPSK, QPSK, 8-PSK) and LDPC coding schemes, and compare against performance over an ideal additive white Gaussian channel. We select a only subset of operating modes to perform the analysis which are based on a number of mitigation techniques to combat the nonlinear distortions. Specifically, transmitter centroidal pre-distortion, phase post-distortion and receiver mean phase estimation are analyzed in this study.

coding↗

NASA NTRS2017

NASA GSFC Report on CCSDS Recommendations 2.1.8A B Minimum Earth Station Transmitter Frequency Resolution for Spacecraft Receiver Acquisition

In Fall 2016, ESA presented paper SLS-RFM 16-10 documenting a possible issue with the frequency lock-in range specification in Recommendation 2.1.8A of typically 267 to 1067 Hz in considerings (b) from considerings (a) for loop bandwidths [2B(sub LO)] in the range of 200 to 800 Hz with a recommendation of 100 Hz step size for frequency sweeping. The paper calculated the lock-in range to be (+/-)266 to (+/-)1064 rad/s or (+/-)42 to (+/-)168 Hz. Also, Recommendation 2.1.8B has the same issue for considering (a) and (b), i.e. for 2B(sub LO) =10 Hz, a lock-in range of 13 Hz was specified and a recommendation of 5 Hz step size for frequency sweeping. ESA also provided test results from the Rosetta and Exomars transponders. The results were somewhat inconsistent since the tests to verify lock-in and pull-in range did not include acquisition time, which is vital to the definition of these performance measures. This paper will address these test results below. However, we first examine the rationale for Recommendation 2.1.8A/B and its consistency with the theory of 2nd order phase lock loop operations. Our approach is to design a digital phase locked loop (DPLL) from phase locked loop (PLL) requirements. All analysis will be performed with a DPLL.

digital phase locked loop↗