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Li, Shuo

Publications and source records attributed to Li, Shuo.

8 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Unraveling sources of emission heterogeneity in Silicon Vacancy color centers with cryo-cathodoluminescence microscopy

Diamond color centers have proven to be versatile quantum emitters and exquisite sensors of stress, temperature, electric and magnetic fields, and biochemical processes. Among color centers, the silicon-vacancy (SiV - ) defect exhibits high brightness, minimal phonon coupling, narrow optical linewidths, and high degrees of photon indistinguishability. Yet the creation of reliable and scalable SiV - -based color centers has been hampered by heterogeneous emission, theorized to originate from surface imperfections, crystal lattice strain, defect symmetry, or other lattice impurities. Here, we advance high-resolution cryo-electron microscopy combined with cathodolumines cence spectroscopy and 4D scanning transmission electron microscopy (STEM) to elucidate the structural sources of heterogeneity in SiV - emission from nanodiamond with sub-nanometer-scale resolution. Our diamond nanoparticles are grown directly on TEM membranes from molecular-level seedings, representing the natural formation conditions of color centers in diamond. We show that individual subcrystallites within a single nanodiamond exhibit distinct zero-phonon line (ZPL) energies and differences in brightness that can vary by 0.1 meV in energy and over 70% in brightness. These changes are correlated with the atomic-scale lattice structure. We find that ZPL blue shifts result from tensile strain, while ZPL red shifts are due to compressive strain. We also find that distinct crystallites host distinct densities of SiV - emitters and that grain boundaries impact SiV - emission significantly. Finally, we interrogate nanodiamonds as small as 40 nm in diameter and show that these diamonds exhibit no spatial change to their ZPL energy. Our work provides a foundation for atomic-scale structure-emission correlation, e.g., of single atomic defects in a range of quantum and two-dimensional materials.

36 MATERIALS SCIENCE↗
DOE OSTI2022

A 194nW Energy-Performance-Aware loT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fast DVFS and Energy Minimization

A self-powered IoT system-on-chip (SoC) reduces power to sub-μw and employs multiple power-management techniques to trade-off ultra-low power (ULP), higher performance, smaller energy harvester footprint, and longer operating lifetime. Minimum Energy Point Tracking (MEPT) [1]–[4] keeps an SoC operating at the minimum energy point (MEP) to enhance system lifetime. Previous sample-and-hold MEPT schemes need frequent voltage comparisons and a high-frequency clock that increases power [2]. Current-ratio-based MEPT relies on specialized CMOS technology for body-bias tuning [3]. A switched-capacitor-based MEPT can achieve energy minimization at a targeted performance [4], but it uses a 30MHz clock witμW power consumption and low power efficiency. For ULP IoT applications, SoCs need to have ultra-low quiescent power, high efficiency for energy delivery, performance scaling based on available energy, and energy minimization to increase system lifetime. In this work, we propose an ULP IoT SoC with a triple-mode power management unit (PMU) that integrates energy-performance scaling, event-driven fast DVFS, and MEPT features to improve the system energy efficiency, as shown in Fig. 13.8.1. This work achieves a minimum 194nW power consumption for the SoC and 5.2nW quiescent power for the PMU with a 92.6% peak efficiency and >10 4 dynamic range. The timing waveform in Fig. 13.8.1 (bottom), demonstrates the transition of the three modes including energy aware (EA), performance aware (PA), and MEPT based on event priority and input voltage level which reflects the energy availability. As such, the system energy consumption and performance could be well-balanced based on both the input and output conditions.

self-powered IoT system-on-chip (SoC)↗
DOE OSTI2022

Au-activated N motifs in non-coherent cupric porphyrin metal organic frameworks for promoting and stabilizing ethylene production

Direct implementation of metal-organic frameworks as the catalyst for CO 2 electroreduction has been challenging due to issues such as poor conductivity, stability, and limited > 2e - products. In this study, Au nanoneedles are impregnated into a cupric porphyrin-based metal-organic framework by exploiting ligand carboxylates as the Au 3+ -reducing agent, simultaneously cleaving the ligand-node linkage. Surprisingly, despite the lack of a coherent structure, the Au-inserted framework affords a superb ethylene selectivity up to 52.5% in Faradaic efficiency, ranking among the best for metal-organic frameworks reported in the literature. Through operando X-ray, infrared spectroscopies and density functional theory calculations, the enhanced ethylene selectivity is attributed to Au-activated nitrogen motifs in coordination with the Cu centers for C-C coupling at the metalloporphyrin sites. Furthermore, the Au-inserted catalyst demonstrates both improved structural and catalytic stability, ascribed to the altered charge conduction path that bypasses the incoherent framework. This study underlines the modulation of reticular metalloporphyrin structure by metal impregnation for steering the CO 2 reduction reaction pathway.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2021

An 802pW 93% Peak Efficiency Buck Converter with 5.5×10 6 Dynamic Range Featuring Fast DVFS and Asynchronous Load-Transient Control

Here this paper presents a buck converter with sub-nW quiescent power, high efficiency, and a wide dynamic range for ultra-low-power (ULP) IoT SoCs. To optimize the SoC power consumption, the buck converter supports fast dynamic voltage and frequency scaling (DVFS) and enables fast load-transient response (FLTR) through asynchronous control. In addition, the buck converter is fully self-contained with all features integrated on chip including a proposed adaptive deadtime controller. Fabricated in 65nm CMOS, measurement results show the buck converter has an 802pW quiescent power at 1.5V input voltage and a 93% peak efficiency. The measured dynamic range is from 0.5nW to 2.75mW, which is over 6 orders of magnitude. The measured voltage droop is 54mV for a 45nA-to-1mA load current step thanks to the asynchronous load-transient detector. The buck converter achieves the highest efficiency and widest dynamic range among all the state-of-the-art sub-nW switching voltage regulators, which makes it well suited for power management in ULP SoCs.

42 ENGINEERING↗
DOE OSTI2020

Spatially resolved fibre cavity ring down spectroscopy

Abstract This paper presents a fibre cavity ring down spectroscopy probed by Rayleigh scattering optical frequency domain reflectometry (OFDR), which provides spatial location of stimuli and improved signal to noise ratio for distributed sensing measurements. A section of optical fibre was integrated into an active fibre ring cavity with optical gain and interrogated by the OFDR system for 11 cycles with a single laser scan. Through the cavity ring down configuration, root-mean-squared (RMS) noise of distributed temperature and strain measurements was reduced to 6.9 mK and less than 0.1 με, respectively for 1-cm spatially resolved measurements. Our work shows that the active fibre cavity configuration can be combined with distributed fibre sensing schemes to achieve both high spatial resolution and high sensitivity measurements.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

An 85 nW IoT Node-Controlling SoC for MELs Power-Mode Management and Phantom Energy Reduction

This paper presents an ultra-low power (ULP) node-controlling system-on-chip (SoC) used for power-mode management and phantom energy reduction of miscellaneous electric loads (MELs). The SoC is powered from a single 2.5 V voltage supply enabled by the integrated power management unit (PMU) and can control up to 16 MELs due to the on-chip 16-channel correlator and the 32b RISC-V microprocessor. To further reduce the system power consumption, two clock domains have been adopted for the correlator and the processor separately. Fabricated in 65-nm CMOS, the measured minimum power consumption of the proposed SoC is only 85 nW at 0.45 V voltage supply and 1 kHz clock frequency. The measured maximum operating frequency can go up to 148 kHz with a 0.55 V supply. An application experiment successfully demonstrates that the SoC controls the power modes of MELs from wake-up to cut-off to save the average power and phantom energy.

power-mode management, phantom energy, phantom pow↗