Engineering topics
Publications and source records attributed to Lipton, Ronald J..
We describe a process flow for a CMOS sensor with intrinsic gain. The design is based on a base wafer which is prepared with closely spaced buried n and p doping layers that form an amplifying high field gain region when the device is biased. A deep n-well forms the collecting electrode. The buried n layer serves to moderate the internal field so that the CMOS transistors within the n-well remain within their operating region.
We describe a detector concept which combines small pixels enabled by 3D sensor-electronics integration with gain produced by a Low Gain Avalanche Diode (LGAD) layer. The detector is double-sided, with electrons collected by the cathode, which provides timing information, and an anode with small pixels to provide position and angle information. The cathode can be coarse grained, providing timing with fewer fast amplifiers to limit power consumption. The anode layer benefits from the gain of the LGAD, with larger signals that also limit the power needed. Position can be reconstructed by measuring the pattern of total charge deposited on the anode. Angle and depth of charge deposit can be measured by the shapes of the anode pulses. We describe a possible assembly technology based on 3D integration.
We report on simulation of single event burnout of low gain avalanche diodes during high voltage operation after irradiation. A model is described which can be used to estimate energy deposition needed for single event burnout and the dependence of burnout on thermal conductivity and thermal resistance to heat sinks.
We summarize TCAD design studies for double sided thick buried layer Low Gain Avalanche Diodes (LGADs). These thick double sided devices introduce new features that require overall optimization. We describe both the parameterized and full process simulation and discuss how the results affect the range of process and LGAD physical parameters.
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