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Liu, K. Y.

Publications and source records attributed to Liu, K. Y..

At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1987

Spacecraft on-board SAR image generation for EOS-type missions

Spacecraft on-board synthetic aperture radar (SAR) image generation is an extremely difficult problem because of the requirements for high computational rates (usually on the order of Giga-operations per second), high reliability (some missions last up to 10 years), and low power dissipation and mass (typically less than 500 watts and 100 Kilograms). Recently, a JPL study was performed to assess the feasibility of on-board SAR image generation for EOS-type missions. This paper summarizes the results of that study. Specifically, it proposes a processor architecture using a VLSI time-domain parallel array for azimuth correlation. Using available space qualifiable technology to implement the proposed architecture, an on-board SAR processor having acceptable power and mass characteristics appears feasible for EOS-type applications.

Liu, K. Y.↗
NASA NTRS1987

Spacecraft on-board SAR processing technology

This paper provides an assessment of the on-board SAR processing technology for Eos-type missions. The proposed Eos SAR sensor and flight data system are introduced, and the SAR processing requirements are described. The SAR on-board SAR processor architecture selection is discussed, and a baseline processor architecture using a frequency-domain processor for range correlation and a modular fault-tolerant VLSI time-domain parallel array for azimuth correlation are described. The mass storage and VLSI technologies needed for implementing the proposed SAR processing are assessed. It is shown that acceptable processor power and mass characteristics should be feasible for Eos-type applications. A proposed development strategy for the on-board SAR processor is presented.

Liu, K. Y.↗
NASA NTRS1986

Modular, Fast, Two-Dimensional Cyclic Convolver

Proposed high-throughput, real-time synthetic-aperture-radar (SAR) processor built using new, modular, two-dimensional cyclic convolver architecture based on polynomial factorization and designed for very-large-scale integrated (VLSI) circuitry. New architecture reduces cost, size, and power dissipation of SAR processor in comparison to high-speed array-processor approach. Processor also used for other image-and data-processing applications involving two-dimensional Fourier transforms.

Liu, K. Y.↗
NASA NTRS1986

Fast Reed-Solomon Decoder

High-speed decoder intended for use with Reed-Solomon (RS) codes of long code length and high error-correcting capability. Design based on algorithm that includes high-radix Fermat transform procedure, which is most efficient for high speeds. RS code in question has code-word length of 256 symbols, of which 224 are information symbols and 32 are redundant.

Liu, K. Y.↗
NASA NTRS1986

Modular VLSI Reed-Solomon Decoder

Proposed Reed-Solomon (RS) decoder assembled from very-large-scale integrated-circuit (VLSI) building blocks. Decoder exploits recursive forms in RS decoding algorithms. RS codes capable of correcting random or burst errors in telemetry and other data-communication signals. Because of small size and low power consumption, advantageous to employ several such decoders in parallel-processing scheme to increase decoding speed.

Liu, K. Y.↗
NASA NTRS1984

Pipelined digital SAR azimuth correlator using hybrid FFT-transversal filter

A synthetic aperture radar system (SAR) having a range correlator is provided with a hybrid azimuth correlator which utilizes a block-pipe-lined fast Fourier transform (FFT). The correlator has a predetermined FFT transform size with delay elements for delaying SAR range correlated data so as to embed in the Fourier transform operation a corner-turning function as the range correlated SAR data is converted from the time domain to a frequency domain. The azimuth correlator is comprised of a transversal filter to receive the SAR data in the frequency domain, a generator for range migration compensation and azimuth reference functions, and an azimuth reference multiplier for correlation of the SAR data. Following the transversal filter is a block-pipelined inverse FFT used to restore azimuth correlated data in the frequency domain to the time domain for imaging.

Wu, C.↗
NASA NTRS1984

Digital SAR Processor

Produces real-time, single-look, high-resolution imagery. Digital synthetic-aperature-radar (SAR) processor achieves rate of 4 million samples per second. System combines frequency-domain and time-domain processing for two-dimensional azimuth correlation.

Wu, C.↗
NASA NTRS1983

VLSI Unit for Two-Dimensional Convolutions

Universal logic structure allows same VLSI chip to be used for variety of computational functions required for two dimensional convolutions. Fast polynomial transform technique is extended into tree computational structure composed of two units: fast polynomial transform (FPT) unit and Chinese remainder theorem (CRT) computational unit.

Liu, K. Y.↗
NASA NTRS1983

VLSI Reed-Solomon Encoder

Modular Reed-solomon encoder uses identical custom VLSI chips called "symbol slices." By cascading and properly interconnecting group of these chips, encoder is made for any desired error-correcting capability and interleaving level. VLSI encoder requires only one-tenth the number of chips required by conventional Reed-Solomon Circuit implemented with discrete IC's.

Liu, K. Y.↗
NASA NTRS1983

A parallel-pipeline architecture of the fast polynomial transform for computing a two-dimensional cyclic convolution

It is pointed out that the two-dimensional cyclic convolution is a useful tool for many two-dimensional digital signal processing applications. Two important applications are related to spaceborne high-resolution synthetic aperture radar (SAR) processing and image processing. Nussbaumer and Quandalle (1978) showed that a radix-2 polynomial transform analogous to the conventional radix-2 FFT algorithm can be used to compute a two-dimensional cyclic convolution. On the basis of results reported by Arambepola and Rayner (1979), a radix-2 polynomial transform can be defined to compute a multidimensional cyclic convolution. Truong et al. (1981) used the considered ideas together with the Chinese Theorem to further reduce the complexity of the radix-2 fast polynomial transform (FPT). Reed et al. (1981) demonstrated that such a new FPT algorithm is significantly faster than the FFT algorithm for computing a two-dimensional convolution. In the present investigation, a parallel-pipeline architecture is considered for implementing the FPT developed by Truong et al.

Truong, T. K.↗
NASA NTRS1982

Modeling and a correlation algorithm for spaceborne SAR signals

A mathematical model of a spaceborne synthetic aperture radar (SAR) response is presented. Thhe associated SAR system performance, in terms of the resolution capability, is also discussed. The analysis of spaceborne SAR target response indicates that the SAR correlation problem is a two-dimensional one with a linear shift-variant response function. A new digital processing algorithm is proposed here in order to realize an economical digital SAR correlation system. The proposed algorithm treats the two-dimensional correlation by a combination of frequency domain fast correlation in the azimuth dimension and a time-domain convolver type of operation in the range dimension. Finally, digitally correlated SEASAT satellite SAR imagery is used in an exemplary sense to validate the SAR response model and the new digital processing technique developed.

Wu, C.↗
NASA NTRS1982

Architecture for VLSI design of Reed-Solomon encoders

A description is given of the logic structure of the universal VLSI symbol-slice Reed-Solomon (RS) encoder chip, from a group of which an RS encoder may be constructed through cascading and proper interconnection. As a design example, it is shown that an RS encoder presently requiring approximately 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical, interconnected VLSI RS encoder chips, offering in addition to greater compactness both a lower power requirement and greater reliability.

Liu, K. Y.↗
NASA NTRS1982

A comparative study of real-time spaceborne synthetic aperture radar processing techniques

A review of various spaceborne synthetic aperture radar (SAR) processing algorithms and their associated real-time SAR processor architectures is given in this paper. The processing complexity for each real-time SAR processor is presented next. A complexity comparison is then given based on the Seasat SAR parameters. It is shown that the frequency/time domain hybrid fast correlation and the two-stage fast Fourier transform (FET) approaches are the two most cost-effective choices for real-time spaceborne SAR processing. Finally, a discussion on future development trends in real-time spaceborne SAR processing is given.

Liu, K. Y.↗
NASA NTRS1981

The effects of receiver tracking phase error on the performance of the concatenated Reed-Solomon/Viterbi channel coding system

Analytical and experimental results are presented of the effects of receiver tracking phase error, caused by weak signal conditions on either the uplink or the downlink or both, on the performance of the concatenated Reed-Solomon (RS) Viterbi channel coding system. The test results were obtained under an emulated S band uplink and X band downlink, two way space communication channel in the telecommunication development laboratory of JPL with data rates ranging from 4 kHz to 20 kHz. It is shown that, with ideal interleaving, the concatenated RS/Viterbi coding system is capable of yielding large coding gains at very low bit error probabilities over the Viterbi decoded convolutional only coding system. Results on the effects of receiver tracking phase errors on the performance of the concatenated coding system with antenna array combining are included.

Liu, K. Y.↗
NASA NTRS1981

An experimental study of the concatenated Reed-Solomon/Viterbi channel coding system performance and its impact on space communications

The need for efficient space communication at very low bit error probabilities to the specification and implementation of a concatenated coding system using an interleaved Reed-Solomon code as the outer code and a Viterbi-decoded convolutional code as the inner code. Experimental results of this channel coding system are presented under an emulated S-band uplink and X-band downlink two-way space communication channel, where both uplink and downlink have strong carrier power. This work was performed under the NASA End-to-End Data Systems program at JPL. Test results verify that at a bit error probability of 10 to the -6 power or less, this concatenated coding system does provide a coding gain of 2.5 dB or more over the Viterbi-decoded convolutional-only coding system. These tests also show that a desirable interleaving depth for the Reed-Solomon outer code is 8 or more. The impact of this "virtually" error-free space communication link on the transmission of images is discussed and examples of simulation results are given.

Liu, K. Y.↗
NASA NTRS1981

Architecture for VLSI design of Reed-Solomon encoders

The logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is discussed. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that a (255,223) RD encoder requiring around 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical interconnected VLSI RS encoder chips. Besides the size advantage, the VLSI RS encoder also has the potential advantages of requiring less power and having a higher reliability.

Liu, K. Y.↗