Liu, Tiehui Ted | Search NASA

DOE OSTI2019

Method and system for high performance real time pattern recognition

Systems and methods supporting high performance real time pattern recognition by including time and regional multiplexing using high bandwidth, board-to-board communications channels, and 3D vertical integration. An array of processing boards can each be coupled a rear transition board, the array achieving time and regional multiplexing using high bandwidth board-to-board communications channels and 3D vertical integration.

42 ENGINEERING↗

DOE OSTI2018

An FPGA-based Pattern Recognition Associative Memory

Pattern recognition associative memory (PRAM) devices are parallel processing engines which are used to tackle the complex combinatorics of track nding algorithms, particularly for silicon based tracking triggers. PRAM development has been mostly limited to the realm of ASICs, which often leads to lengthy and expensive design cycles. FPGAs allow for quick iterations, making them an ideal hardware platform for designing and evaluating new PRAM features before committing to silicon. In this paper we present our FPGA-based PRAM designs and discuss how logic blocks which were originally developed for ASICs have been redesigned to take advantage of modern FPGA architectures.

43 PARTICLE ACCELERATORS↗