Manna, Bibhas | Search NASA

DOE OSTI2024

Device Feasibility Analysis of Multi-level FeFETs for Neuromorphic Computing

As an emerging non-volatile memory device technology, Ferroelectric Field-Effect Transistors (FeFETs) can enable low-power, adaptive intelligent system design. However, device dimension and operating voltage dependent reliability issues of scaled FeFETs can ultimately lead to degraded performance in solving machine learning tasks. In this article, detailed experimental characterization of FeFET devices of different dimensions have been carried out to explicitly evaluate the non-ideal behavior in device conductance programming properties like number of programming states, cycle-to-cycle (C2C) variations, device-to-device (D2D) variations, and state retention. A hardware-aware software simulation approach has been adopted to capture the adversarial effects of the non-idealities on recognition accuracy through algorithm-level performance assessment by including them in NeuroSim, a popular neural network hardware simulator, to execute a neural network model considering all other hardware constraints. With the added non-idealities, significant accuracy degradation has been observed compared to the ideal scenarios where D2D variations play the most critical role. Thereafter, feasibility of a variation-aware training method has been evaluated to tackle the accuracy drop.

42 ENGINEERING↗

DOE OSTI2024

Variation-Resilient FeFET-Based In-Memory Computing Leveraging Probabilistic Deep Learning

Reliability issues stemming from device level nonidealities of nonvolatile emerging technologies like ferroelectric field-effect transistors (FeFETs), especially at scaled dimensions, cause substantial degradation in the accuracy of in-memory crossbar-based AI systems. Here, in this work, we present a variation-aware design technique to characterize the device level variations and to mitigate their impact on hardware accuracy employing a Bayesian neural network (BNN) approach. An effective conductance variation model is derived from the experimental measurements of cycle-to-cycle (C2C) and device-to-device (D2D) variations performed on FeFET devices fabricated using 28 nm high-k metal gate technology. The variations were found to be a function of different conductance states within the given programming range, which sharply contrasts earlier efforts where a fixed variation dispersion was considered for all conductance values. Such variation characteristics formulated for three different device sizes at different read voltages were provided as prior variation information to the BNN to yield a more exact and reliable inference. Near-ideal accuracy for shallow networks (MLP5 and LeNet models) on the MNIST dataset and limited accuracy decline by ~3.8%–16.1% for deeper AlexNet models on CIFAR10 dataset under a wide range of variations corresponding to different device sizes and read voltages, demonstrates the efficacy of our proposed device-algorithm co-design technique.

97 MATHEMATICS AND COMPUTING↗