Engineering topics

Miryala, S

Publications and source records attributed to Miryala, S.

4 records

DOE OSTI2025

RD53 pixel readout integrated circuits for ATLAS and CMS HL-LHC upgrades

The RD53 collaboration has since 2013 developed new hybrid pixel detector chips with 50 × 50 μm2 pixels for the HL-LHC upgrades of the ATLAS and CMS experiments at CERN. A common architecture, design and verification framework has been developed to enable final pixel chips of different sizes to be designed, verified and tested to handle extreme hit rates of 3 GHz/cm2 (up to 12 GHz per chip) together with an increased trigger rate of 1 MHz and efficient readout of up to 5.12 Gbits/s per pixel chip. Tolerance to an extremely hostile radiation environment with 1 Grad over 10 years and induced SEU (Single Event Upset) rates of up to 100 upsets per second per chip have been major challenges to make reliable pixel chips. Three generations of pixel chips, and many specific mixed signal building blocks and radiation test chips, have been submitted and extensively tested to get to final production chips. The large, complex and high rate pixel chips have been developed with a strong emphasis on low power consumption together with a concurrent development and qualification of novel serial powering at chip, module and system level, to minimize detector material budget.

Alimonti, G↗

DOE OSTI2022

Investigation of Timing Properties for an Event Driven with Access and Reset Decoder Readout Architecture for a Pixel Array

The large number of data generating sources (data channels) on a single chip requires appropriate techniques to manage a readout from these channels. One of the main methods is sharing a medium of transmission, which requires arbitration to avoid collisions or deadlocks. Existing solutions face several problems such as a dead time, unintended prioritization or metastability. That is why we decided to create a new readout architecture named EDWARD i.e., Event Driven with Access and Reset Decoder. The EDWARD architecture gets rid of the earlier mentioned problems and mitigates the other ones. However, due to the use of logic circuits outside a standard cell library, which are hard to characterize, we were challenged to perform an additional transient analysis to validate the architecture. Here we show a methodology and the results of the simulations. Based on the results obtained we can confirm the functional correctness of the system and plan the optimization of operating conditions in order to achieve better performance. Our goal is to use the EDWARD architecture in the future radiation detectors to be built at Brookhaven National Laboratory.

47 OTHER INSTRUMENTATION↗

DOE OSTI2022

Event driven readout architecture with non-priority arbitration for radiation detectors

A novel event driven readout architecture, EDWARD (Event Driven with Access and 8 Reset Decoder) architecture, for highly granular pixel detectors is presented. It incorporates, inter alia, an asynchronous arbitration tree based on Seitz' arbiters, removing the need for an imposed prioritization scheme. It also provides protection against glitches during readout. The system allows not only reading pixel activities, but also retrieving additional data, both analog and digital, from the pixels. A novel in-channel logic allows the entire readout process to be split into consecutive phases for additional flexibility. All operations are controlled by only one edge of the clock signal, seen as an acknowledge token, so there is no dead time between readouts.

47 OTHER INSTRUMENTATION↗

DOE OSTI2020

A 1.2-V 6-GHz Dual-Path Charge-Pump PLL Frequency Synthesizer for Quantum Control and Readout in CMOS 65-nm Process

This paper presents a low jitter dual-path chargepump phase locked loop (PLL) synthesizer in a CMOS 65-nm process for quantum readout applications. The PLL incorporates a programmable dual chargepump and a loop filter with both proportional and integral paths that can be driven independently providing flexible control of the loop bandwidth to achieve low jitter performance. The design is implemented at 300 K and critical blocks like voltage-controlled oscillator (VCO) and chargepump (CP) are analyzed at 77 K based on the characterized results. The LC-VCO is realized with the class-C NMOS only architecture with 5-bit coarse control and quadrature signals are generated with poly phase filter. The VCO is designed with the tuning range of 1 GHz around the center frequency of 6 GHz with Phase Noise of -123 dBc/Hz and -132 dBc/Hz at 1MHz offset at 300 K and 77 K temperature. The simulated PLL rms jitter is 125 fs at 6 GHz with a power consumption of 8 mW at the 1.2 V power supply.

47 OTHER INSTRUMENTATION↗