Engineering topics

Mohamed, Mohamed

Publications and source records attributed to Mohamed, Mohamed.

4 records

DOE OSTI2024

Giant energy storage and power density negative capacitance superlattices

Dielectric electrostatic capacitors, because of their ultrafast charge-discharge, are desirable for high-power energy storage applications. Along with ultrafast operation, on-chip integration can enable miniaturized energy storage devices for emerging autonomous microelectronics and microsystems. Moreover, state-of-the-art miniaturized electrochemical energy storage systems-microsupercapacitors and microbatteries-currently face safety, packaging, materials and microfabrication challenges preventing on-chip technological readiness, leaving an opportunity for electrostatic microcapacitors. Here, in this study, we report record-high electrostatic energy storage density (ESD) and power density, to our knowledge, in HfO 2 -ZrO 2 -based thin film microcapacitors integrated into silicon, through a three-pronged approach. First, to increase intrinsic energy storage, atomic-layer-deposited antiferroelectric HfO 2 -ZrO 2 films are engineered near a field-driven ferroelectric phase transition to exhibit amplified charge storage by the negative capacitance effect, which enhances volumetric ESD beyond the best-known back-end-of-the-line-compatible dielectrics (115 J cm -3 ). Second, to increase total energy storage, antiferroelectric superlattice engineering scales the energy storage performance beyond the conventional thickness limitations of HfO 2 -ZrO 2 -based (anti)ferroelectricity (100-nm regime). Third, to increase the storage per footprint, the superlattices are conformally integrated into three-dimensional capacitors, which boosts the areal ESD nine times and the areal power density 170 times that of the best-known electrostatic capacitors: 80 mJ cm -2 and 300 kW cm -2 , respectively. This simultaneous demonstration of ultrahigh energy density and power density overcomes the traditional capacity-speed trade-off across the electrostatic-electrochemical energy storage hierarchy. Furthermore, the integration of ultrahigh-density and ultrafast-charging thin films within a back-end-of-the-line-compatible process enables monolithic integration of on-chip microcapacitors, which can unlock substantial energy storage and power delivery performance for electronic microsystems.

25 ENERGY STORAGE↗

DOE OSTI2023

Low-thermal-budget synthesis of monolayer molybdenum disulfide for silicon back-end-of-line integration on a 200 mm platform

Two-dimensional (2D) materials are promising candidates for future electronics due to their excellent electrical and photonic properties. Although promising results on the wafer-scale synthesis (≤150 mm diameter) of monolayer molybdenum disulfide (MoS 2 ) have already been reported, the high-quality synthesis of 2D materials on wafers of 200 mm or larger, which are typically used in commercial silicon foundries, remains difficult. The back-end-of-line (BEOL) integration of directly grown 2D materials on silicon complementary metal–oxide–semiconductor (CMOS) circuits is also unavailable due to the high thermal budget required, which far exceeds the limits of silicon BEOL integration (<400 °C). This high temperature forces the use of challenging transfer processes, which tend to introduce defects and contamination to both the 2D materials and the BEOL circuits. Here we report a low-thermal-budget synthesis method (growth temperature < 300 °C, growth time ≤ 60 min) for monolayer MoS 2 films, which enables the 2D material to be synthesized at a temperature below the precursor decomposition temperature and grown directly on silicon CMOS circuits without requiring any transfer process. We designed a metal–organic chemical vapour deposition reactor to separate the low-temperature growth region from the high-temperature chalcogenide-precursor-decomposition region. We obtain monolayer MoS 2 with electrical uniformity on 200 mm wafers, as well as a high material quality with an electron mobility of ~35.9 cm 2 V -1 s -1 . Finally, we demonstrate a silicon-CMOS-compatible BEOL fabrication process flow for MoS 2 transistors; the performance of these silicon devices shows negligible degradation (current variation < 0.5%, threshold voltage shift < 20 mV). We believe that this is an important step towards monolithic 3D integration for future electronics.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

DOE OSTI2022

On the Feasibility of 1T Ferroelectric FET Memory Array

To fully exploit the ferroelectric field effect transistor (FeFET) as compact embedded nonvolatile memory for various computing and storage applications, it is desirable to use a single FeFET (1T) as a unit cell and arrange the cells into an array. However, many write mechanisms for an 1T FeFET array reported in the literature are yet to be validated experimentally. In this work, we performed a comprehensive experimental characterization on the write operations in an 1T- NOR and 1T- AND array using n-channel bulk FeFETs. We discovered that: 1) the source/drain contact can only supply minority carriers (i.e., electrons) to the channel for polarization screening during the low- V TH state programming; 2) the body contact can not only supply majority carriers (i.e., holes) for efficient high- V TH state write, but also depletion charge for low- V TH state programming, though with lower efficiency; and 3) during the low/high- V TH programming, only the path that can supply negative/positive screening charges, respectively, need to respond, which necessitates the application of proper write biases on the corresponding terminal. Based on the understanding of these write mechanisms, we show the importance of localized body contact or column-wise body contact for the successful high- V TH state programming. We also show that the previously proposed C- AND write scheme fails to program the FeFET to the low- V TH state for our devices. Finally, we propose several write schemes for both 1T- AND and 1T- NOR arrays for various scenarios providing insights for choosing the appropriate write scheme, which will facilitate the adoption of 1T FeFET memory arrays for emerging applications.

FeFET↗

DOE OSTI2022

Ultrathin ferroic HfO 2 –ZrO 2 superlattice gate stack for advanced transistors

With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage. This led to a fundamental change in the gate stack in 2008, the incorporation of high-dielectric-constant HfO 2 , which remains the material of choice to date. Here we report HfO 2 –ZrO 2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric–antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal–oxide–semiconductor capacitors is equivalent to an effective SiO 2 thickness of approximately 6.5 ångströms. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO 2 -based high-dielectric-constant gate stacks without scavenging the interfacial SiO 2 , which has adverse effects on the electron transport and gate leakage current. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. This work demonstrates that ultrathin ferroic HfO 2 –ZrO 2 multilayers, stabilized with competing ferroelectric–antiferroelectric order in the two-nanometre-thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO 2 -based high-dielectric-constant materials.

36 MATERIALS SCIENCE↗