Engineering topics

Nelson, Dave

Publications and source records attributed to Nelson, Dave.

2 records

DOE OSTI2022

Fatigue performance of laser powder bed fusion hydride-dehydride Ti-6Al-4V powder

We report hydride-dehydride (HDH) Ti-6Al-4V alloy with particle size distribution of 50–120 µm is laser powder bed fusion (L-PBF) processed using optimum processing parameters and a near-fully dense structure with a density of 99.9 % is achieved. Microstructural observations and phase analyses indicate formation of columnar β grains with acicular α/α' phases in as-built condition. The roughness of the as-fabricated samples is significant with an average roughness of R a = 15.71 ± 3.96 µm and a root mean square roughness of R rms = 108.4 ± 24.9 µm, however, both values are reduced to R a = 0.19 ± 0.04 µm and R rms = 4.9 ± 0.6 µm after mechanical grinding. Mechanical tests are carried out on as-fabricated specimens followed by stress relief treatment. All samples are tested to failure in fatigue, under fully-reversed tension-compression conditions of R = –1. The as-built samples failed from the surface with crack initiation mainly at micro-notches, whereas after mechanically grinding, crack initiation changed to subsurface defects such as pores. Minimizing surface roughness by mechanically grinding eliminates surface micro-notches which improves fatigue strength in the high cycle fatigue region. Fatigue notch factor calculations showed that the effect of surface roughness was significantly lower when HDH powder is used compared to standard spherical powder. X-ray diffraction analysis revealed an in-plane compressive stress, micro-strain and grain refinement on the surface of the mechanically ground samples. Fractography observations (macroscale) revealed a fully brittle fracture in the first stage of crack growth with a transition to a dominantly ductile fracture in the third stage of crack growth. On the other hand, at the micro scale, even the brittle fracture regions showed evidence of ductile fracture within the α' martensite laths.

36 MATERIALS SCIENCE↗

NASA NTRS2014

Centering a DDR Strobe in the Middle of a Data Packet

The Orion CEV Northstar ASIC (application- specific integrated circuit) project required a DDR (double data rate) memory bus driver/receiver (DDR PHY block) to interface with external DDR memory. The DDR interface (JESD79C) is based on a source synchronous strobe (DQS\) that is sent along with each packet of data (DQ). New data is provided concurrently with each edge of strobe and is sent irregularly. In order to capture this data, the strobe needs to be delayed and used to latch the data into a register. A circuit solves the need for training a DDR PRY block by incorporating a PVT-compensated delay element in the strobe path. This circuit takes an external reference clock signal and uses the regular clock to calibrate a known delay through a data path. The compensated delay DQS signal is then used to capture the DQ data in a normal register. This register structure can be configured as a FIFO (first in first out), in order to transfer data from the DDR domain to the system clock domain. This design is different in that it does not rely upon the need for training the system response, nor does it use a PLL (phase locked loop) or a DLL (delay locked loop) to provide an offset of the strobe signal. The circuit is created using standard ASIC building blocks, plus the PVT (process, voltage, and temperature) compensated delay line. The design uses a globally available system clock as a reference, alleviating the need to operate synchronously with the remote memory. The reference clock conditions the PVT compensated delay line to provide a pre-determined amount of delay to any data signal that passes through this delay line. The delay line is programmed in degrees of offset, so that one could think of the clock period representing 360deg of delay. In an ideal environment, delaying the strobe 1/4 of a clock cycle (90deg) would place the strobe in the middle of the data packet. This delayed strobe can then be used to clock the data into a register, satisfying setup and hold requirements of the system.

Johnson, Michael↗