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Ni, Kai

Publications and source records attributed to Ni, Kai.

At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Device Feasibility Analysis of Multi-level FeFETs for Neuromorphic Computing

As an emerging non-volatile memory device technology, Ferroelectric Field-Effect Transistors (FeFETs) can enable low-power, adaptive intelligent system design. However, device dimension and operating voltage dependent reliability issues of scaled FeFETs can ultimately lead to degraded performance in solving machine learning tasks. In this article, detailed experimental characterization of FeFET devices of different dimensions have been carried out to explicitly evaluate the non-ideal behavior in device conductance programming properties like number of programming states, cycle-to-cycle (C2C) variations, device-to-device (D2D) variations, and state retention. A hardware-aware software simulation approach has been adopted to capture the adversarial effects of the non-idealities on recognition accuracy through algorithm-level performance assessment by including them in NeuroSim, a popular neural network hardware simulator, to execute a neural network model considering all other hardware constraints. With the added non-idealities, significant accuracy degradation has been observed compared to the ideal scenarios where D2D variations play the most critical role. Thereafter, feasibility of a variation-aware training method has been evaluated to tackle the accuracy drop.

42 ENGINEERING↗
DOE OSTI2024

Variation-Resilient FeFET-Based In-Memory Computing Leveraging Probabilistic Deep Learning

Reliability issues stemming from device level nonidealities of nonvolatile emerging technologies like ferroelectric field-effect transistors (FeFETs), especially at scaled dimensions, cause substantial degradation in the accuracy of in-memory crossbar-based AI systems. Here, in this work, we present a variation-aware design technique to characterize the device level variations and to mitigate their impact on hardware accuracy employing a Bayesian neural network (BNN) approach. An effective conductance variation model is derived from the experimental measurements of cycle-to-cycle (C2C) and device-to-device (D2D) variations performed on FeFET devices fabricated using 28 nm high-k metal gate technology. The variations were found to be a function of different conductance states within the given programming range, which sharply contrasts earlier efforts where a fixed variation dispersion was considered for all conductance values. Such variation characteristics formulated for three different device sizes at different read voltages were provided as prior variation information to the BNN to yield a more exact and reliable inference. Near-ideal accuracy for shallow networks (MLP5 and LeNet models) on the MNIST dataset and limited accuracy decline by ~3.8%–16.1% for deeper AlexNet models on CIFAR10 dataset under a wide range of variations corresponding to different device sizes and read voltages, demonstrates the efficacy of our proposed device-algorithm co-design technique.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Ferroelectric FET-based context-switching FPGA enabling dynamic reconfiguration for adaptive deep learning machines

Field programmable gate array (FPGA) is widely used in the acceleration of deep learning applications because of its reconfigurability, flexibility, and fast time-to-market. However, conventional FPGA suffers from the trade-off between chip area and reconfiguration latency, making efficient FPGA accelerations that require switching between multiple configurations still elusive. Here, we propose a ferroelectric field-effect transistor (FeFET)–based context-switching FPGA supporting dynamic reconfiguration to break this trade-off, enabling loading of arbitrary configuration without interrupting the active configuration execution. Leveraging the intrinsic structure and nonvolatility of FeFETs, compact FPGA primitives are proposed and experimentally verified. The evaluation results show our design shows a 63.0%/74.7% reduction in a look-up table (LUT)/connection block (CB) area and 82.7%/53.6% reduction in CB/switch box power consumption with a minimal penalty in the critical path delay (9.6%). Besides, our design yields significant time savings by 78.7 and 20.3% on average for context-switching and dynamic reconfiguration applications, respectively.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Embedding security into ferroelectric FET array via in situ memory operation

Non-volatile memories (NVMs) have the potential to reshape next-generation memory systems because of their promising properties of near-zero leakage power consumption, high density and non-volatility. However, NVMs also face critical security threats that exploit the non-volatile property. Compared to volatile memory, the capability of retaining data even after power down makes NVM more vulnerable. Existing solutions to address the security issues of NVMs are mainly based on Advanced Encryption Standard (AES), which incurs significant performance and power overhead. In this paper, we propose a lightweight memory encryption/decryption scheme by exploiting in-situ memory operations with negligible overhead. To validate the feasibility of the encryption/decryption scheme, device-level and array-level experiments are performed using ferroelectric field effect transistor (FeFET) as an example NVM without loss of generality. Besides, a comprehensive evaluation is performed on a 128 × 128 FeFET AND-type memory array in terms of area, latency, power and throughput. Compared with the AES-based scheme, our scheme shows ~22.6×/~14.1× increase in encryption/decryption throughput with negligible power penalty. Furthermore, we evaluate the performance of our scheme over the AES-based scheme when deploying different neural network workloads. Our scheme yields significant latency reduction by 90% on average for encryption and decryption processes.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

Hybrid stochastic synapses enabled by scaled ferroelectric field-effect transistors

Achieving brain-like density and performance in neuromorphic computers necessitates scaling down the size of nanodevices emulating neuro-synaptic functionalities. However, scaling nanodevices results in reduction of programming resolution and emergence of stochastic non-idealities. While prior work has mainly focused on binary transitions, in this work, we leverage the stochastic switching of a three-state ferroelectric field-effect transistor to implement a long-term and short-term two-tier stochastic synaptic memory with a single device. Experimental measurements are performed on a scaled 28 nm high-k metal gate technology-based device to develop a probabilistic model of the hybrid stochastic synapse. In addition to the advantage of ultra-low programming energies afforded by scaling, our hardware–algorithm co-design analysis reveals the efficacy of the two-tier memory in comparison to binary stochastic synapses in on-chip learning tasks—paving the way for algorithms exploiting multi-state devices with probabilistic transitions beyond deterministic ones.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2023

Compact Ferroelectric Programmable Majority Gate for Compute-in-Memory Applications

In this study, a compact and novel ferroelectric (FE) programmable majority gate is proposed and its novel application in Binary Neural Network (BNNs) is investigated. We demonstrate: i) by integrating N metal-ferroelectric-metal (MFM) capacitors on the gate of a transistor (1T-N-MFM structure), a nonvolatile and programmable majority (MAJ) gate that performs MAJ of AND between the gate input and polarization is realized; ii) validation the functionality of our 3-input MAJ of AND gate through comprehensive theoretical and experimental investigations; iii) a compact implementation of 3-input MAJ of XNOR gate that leverages only five of our 3-input MAJ of AND gates connected in parallel; iv) application of MAJ of XNOR gates to replace the XNOR gates and the first layer of the adder tree in the BNNs for up to 21x area saving on top of eliminating the energy-hungry memory accesses due to the compute-in-memory nature.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Ferroelectric 2D antimony oxides with wide bandgaps

The first two-dimensional (2D) polymorphs of antimony dioxide, namely, γ-Sb 2 O 4 and δ-Sb 2 O 4 , are predicted using the evolutionary algorithm combined with first-principles density functional theory (DFT) calculations. Out-of-plane ferroelectricity is found in γ-Sb 2 O 4 , while in-plane ferroelectricity is found in δ-Sb 2 O 4 . The predicted dipole moments of γ-Sb 2 O 4 and δ-Sb 2 O 4 phases are 36.63 and 14.96 eÅ, respectively, implying that they can be good candidates for making ferroelectric devices. Further, the calculations show that doping with other group V elements or applying strain can lower the switching energy barriers and thus facilitate switching. Results from GW calculations show indirect band gaps of 5.51 and 3.39 eV for γ-Sb 2 O 4 and δ-Sb 2 O 4 in their monolayers, respectively. Raman spectra are calculated to facilitate the experimental investigation of the predicted structures. The existence of both in-plane and out-of-plane 2D ferroelectricity and the large band gaps make this material system particularly interesting for potential applications.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2022

On the Feasibility of 1T Ferroelectric FET Memory Array

To fully exploit the ferroelectric field effect transistor (FeFET) as compact embedded nonvolatile memory for various computing and storage applications, it is desirable to use a single FeFET (1T) as a unit cell and arrange the cells into an array. However, many write mechanisms for an 1T FeFET array reported in the literature are yet to be validated experimentally. In this work, we performed a comprehensive experimental characterization on the write operations in an 1T- NOR and 1T- AND array using n-channel bulk FeFETs. We discovered that: 1) the source/drain contact can only supply minority carriers (i.e., electrons) to the channel for polarization screening during the low- V TH state programming; 2) the body contact can not only supply majority carriers (i.e., holes) for efficient high- V TH state write, but also depletion charge for low- V TH state programming, though with lower efficiency; and 3) during the low/high- V TH programming, only the path that can supply negative/positive screening charges, respectively, need to respond, which necessitates the application of proper write biases on the corresponding terminal. Based on the understanding of these write mechanisms, we show the importance of localized body contact or column-wise body contact for the successful high- V TH state programming. We also show that the previously proposed C- AND write scheme fails to program the FeFET to the low- V TH state for our devices. Finally, we propose several write schemes for both 1T- AND and 1T- NOR arrays for various scenarios providing insights for choosing the appropriate write scheme, which will facilitate the adoption of 1T FeFET memory arrays for emerging applications.

FeFET↗
DOE OSTI2022

Hardware functional obfuscation with ferroelectric active interconnects

Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-complexity with significant area, energy, and delay penalty. In this paper, we propose an efficient hardware encryption technique with minimal complexity and overheads based on ferroelectric field-effect transistor (FeFET) active interconnects. By utilizing the threshold voltage programmability of the FeFETs, run-time reconfigurable inverter-buffer logic, utilizing two FeFETs and an inverter, is enabled. Judicious placement of the proposed logic makes it act as a hardware encryption key and enable encoding and decoding of the functional output without affecting the critical path timing delay. Additionally, a peripheral programming scheme for reconfigurable logic by reusing the existing scan chain logic is proposed, obviating the need for specialized programming logic and circuitry for keybit distribution. Our analysis shows an average encryption probability of 97.43% with an increase of 2.24%/ 3.67% delay for the most critical path/ sum of 100 critical paths delay for ISCAS85 benchmarks.

42 ENGINEERING↗
DOE OSTI2021

Intrinsic synaptic plasticity of ferroelectric field effect transistors for online learning

Nanoelectronic devices emulating neuro-synaptic functionalities through their intrinsic physics at low operating energies is imperative toward the realization of brain-like neuromorphic computers. In this work, we leverage the non-linear voltage dependent partial polarization switching of a ferroelectric field effect transistor to mimic plasticity characteristics of biological synapses. Here, we provide experimental measurements of the synaptic characteristics for a 28nm high-k metal gate technology based device and develop an experimentally calibrated device model for large-scale system performance prediction. Decoupled read-write paths, ultra-low programming energies and the possibility of arranging such devices in a cross-point architecture demonstrate the synaptic efficacy of the device. Our hardware-algorithm co-design analysis reveals that the intrinsic plasticity of the ferroelectric devices has potential to enable unsupervised local learning in edge devices with limited training data

42 ENGINEERING↗
DOE OSTI2021

Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on the Device Variation of Ferroelectric FET

In this work, a comprehensive study of random spatial fluctuation of the ferroelectric (FE) phase and dielectric (DE) phase in FeFETs is conducted to understand its impact on device variation. It is found that: i) there exists a certain DE percentage threshold that below which the increase of the DE phase does not significantly impact the device memory window and variation and only above which evident device degradation can be observed; ii) increasing the DE phase increases the variation in the memory window and the coercive field distribution further exacerbates the variation, hence degrading the sensing margin; iii) decreasing the number of grains degrades the device variation, which calls for further grain size engineering for variation suppression.

42 ENGINEERING↗
DOE OSTI2018

A Fundamental Frequency Sorting Algorithm for Capacitor Voltage Balance of Modular Multilevel Converter With Low-Frequency Carrier Phase Shift Modulation

This paper proposes a fundamental frequency sorting algorithm for balancing the floating capacitors in modular multilevel converters with low-frequency carrier phase shift modulation. The relationship between the driving pulses and submodules (SMs) is rebuilt in every fundamental period by sorting the voltage increments and present voltages. Besides, an improved and simplified strategy is proposed to predict the charging abilities of the driving pulses, so as to avoid sorting the voltage increments. Based on the proposed method, the switching frequency of each power device and the carrier frequency are identical, which reduces the operational losses for applications regarding high power. At the same time, the sorting frequency is as low as the fundamental frequency, which alleviates a large amount of computational cost, and the necessity to measure arm currents is omitted. In this case, the arm current sensors are eliminated, and simplified communication among the central controller and the local ones is set up. Finally, a three-phase 1-MVA simulation platform with 120 SMs and a down-scaled 6-kVA experimental prototype with 48 SMs are constructed to validate the proposed approach.

42 ENGINEERING↗
DOE OSTI2018

Silicon compatible Sn-based resistive switching memory

Large banks of cheap, fast, non-volatile, energy efficient, scalable solid-state memories are an increasingly essential component for today's data intensive computing. Conductive-bridge random access memory (CBRAM) – which involves voltage driven formation and dissolution of Cu or Ag filaments in a Cu (or Ag) anode/dielectric (HfO 2 or Al 2 O 3 )/inert cathode device – possesses the necessary attributes to fit the requirements. Cu and Ag are, however, fast diffusers and known contaminants in silicon microelectronics. In this paper, employing a criterion for electrode metal selection applicable to cationic filamentary devices and using first principles calculations for estimating diffusion barriers in HfO 2 , we identify tin (Sn) as a rational, silicon CMOS compatible replacement for Cu and Ag anodes in CBRAM devices. We then experimentally fabricate Sn based CBRAM devices and demonstrate very fast, steep-slope memory switching as well as threshold switching, comparable to Cu or Ag based devices. Furthermore, time evolution of the cationic filament formation along with the switching mechanism is discussed based on time domain measurements (I vs. t) carried out under constant voltage stress. Finally, the time to threshold is shown to be a function of both the voltage stress (V stress ) as well as the initial leakage current (I 0 ) through the device.

42 ENGINEERING↗
DOE OSTI2018

The Fault Detection, Localization, and Tolerant Operation of Modular Multilevel Converters with an Insulated Gate Bipolar Transistor (IGBT) Open Circuit Fault

Reliability is one of the critical issues for a modular multilevel converter (MMC) since it consists of a large number of series-connected power electronics submodules (SMs). Here in this paper, a complete control strategy including fault detection, localization, and tolerant operation is proposed for the MMC under an insulated gate bipolar transistor (IGBT) open circuit fault. According to the output characteristics of the SM with the open-circuit fault of IGBT, a fault detection method based on the circulating current and output current observation is used. In order to further precisely locate the position of the faulty SM, a fault localization method based on the SM capacitor voltage observation is developed. After the faulty SM is isolated, the continuous operation of the converter is ensured by adopting the fault-tolerant strategy based on the use of redundant modules. To verify the proposed fault detection, fault localization, and fault-tolerant operation strategies, a 900 kVA MMC system under the conditions of an IGBT open circuit is developed in the Matlab/Simulink platform. The capabilities of rapid detection, precise positioning, and fault-tolerant operation of the investigated detection and control algorithms are also demonstrated.

42 ENGINEERING↗
DOE OSTI2017

Memristive devices from ZnO nanowire bundles and meshes

Here, we report two types of memristive devices made of ZnO nanowire assemblies and Ag electrodes: nanowire-bundle and nanowire-mesh memristors. Although constructed with the same materials, these devices exhibit different characteristics. Nanowire-bundle memristors have small On/Off ratios and feature stable hysteresis under X-ray irradiation. Nanowire-mesh memristors show large On/Off ratios and multiple distinct states. We attribute the switching in bundle nanowires to the modification of the Schottky barrier by the mobile Ag ions and the stability of hysteresis to the ability of the bundles to retain Ag in the alleys between nanowires, as confirmed by first-principles calculations and energy dispersive x-ray measurements. For nanowire-mesh memristors, the high On/Off ratio leads us to attribute the switching mechanism to the formation and dissolution of Ag bridges in the nano-gaps at the intersections of nanowires.

42 ENGINEERING↗
DOE OSTI2017

Direct Analysis of Organic Compounds in Liquid Using a Miniature Photoionization Ion Trap Mass Spectrometer with Pulsed Carrier-Gas Capillary Inlet

A miniature ion trap mass spectrometer with capillary direct sampling and vacuum ultraviolet photoionization source was developed to conduct trace analysis of organic compounds in liquids. Self-aspiration sampling is available where the samples are drawn into the vacuum chamber through a capillary with an extremely low flow rate (less than 1 μL/min), which minimizes sample consumption in each analysis to tens of micrograms. A pulsed gas-assisted inlet was designed and optimized to promote sample transmission in the tube and facilitate the cooling of ions, thereby improving instrument sensitivity. A limit of detection of 2 ppb could be achieved for 2,4-dimethylaniline in a methanol solution. The sampling system described in the present study is specifically suitable for a miniature photoionization ion trap mass spectrometer that can perform rapid and online analysis for liquid samples. .

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗