Phase I Final Technical Report on Energy-Efficient Reconfigurable Universal Accelerator Interconnect
It is well known that application specific computing systems, optimally designed and configured for a given workload, offer much higher energy-efficiency and throughput than general purpose systems. In modern computing systems, heterogeneous computing systems have emerged that exploit the energy and performance benefits of combining various different domain-specific processor architectures. Application domains such as high-performance computing and machine learning now process terabyte-sized data sets, requiring enormous processing and memory resources. These applications have very high-power consumption due to bottlenecks in the electrical interconnection between processing units. This project aims to reduce both communication energy and latency by integrating universally available accelerators with silicon photonics. It also aims to increase system throughput by exploiting emerging technologies in silicon photonic reconfigurable interconnects; this will allow the system to balance itself in real time to accommodate changes in workloads and data flows.